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authorRichard Henderson <rth@cygnus.com>1998-01-21 17:44:04 -0800
committerRichard Henderson <rth@gcc.gnu.org>1998-01-21 17:44:04 -0800
commit84303d9a68d0aef3b30c426ac7183cf3afb449d3 (patch)
tree8b6cc28c82e2316ac6aea0039e1e47c65f82e887
parent48464ebfeff168d33da2c7a7dc76bb4cee77fcdc (diff)
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alpha.md (abssf2, absdf2): Disable in IEEE mode.
* alpha.md (abssf2, absdf2): Disable in IEEE mode. (negsf2, negdf2): Use proper subtract in IEEE mode. From-SVN: r17440
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/alpha/alpha.md38
2 files changed, 40 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d791f3a..9f3aa4d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+Thu Jan 22 01:40:52 1998 Richard Henderson <rth@cygnus.com>
+
+ * alpha.md (abssf2, absdf2): Disable in IEEE mode.
+ (negsf2, negdf2): Use proper subtract in IEEE mode.
+
Tue Jan 20 09:29:09 1998 Jeffrey A Law (law@cygnus.com)
* Makefile.in: Remove more bytecode stuff.
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 2e36e05..71ae3fd 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -1620,24 +1620,40 @@
(define_insn "abssf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm == ALPHA_FPTM_N"
"cpys $f31,%R1,%0"
[(set_attr "type" "fcpys")])
(define_insn "absdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm == ALPHA_FPTM_N"
"cpys $f31,%R1,%0"
[(set_attr "type" "fcpys")])
(define_insn "negsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm == ALPHA_FPTM_N"
"cpysn %R1,%R1,%0"
[(set_attr "type" "fadd")])
+(define_insn ""
+ [(set (match_operand:SF 0 "register_operand" "=&f")
+ (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+ "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+ "sub%,%)%& $f31,%R1,%0"
+ [(set_attr "type" "fadd")
+ (set_attr "trap" "yes")])
+
+(define_insn ""
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+ "TARGET_FP"
+ "sub%,%)%& $f31,%R1,%0"
+ [(set_attr "type" "fadd")
+ (set_attr "trap" "yes")])
+
(define_insn "negdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
@@ -1646,6 +1662,22 @@
[(set_attr "type" "fadd")])
(define_insn ""
+ [(set (match_operand:DF 0 "register_operand" "=&f")
+ (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+ "sub%-%)%& $f31,%R1,%0"
+ [(set_attr "type" "fadd")
+ (set_attr "trap" "yes")])
+
+(define_insn ""
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+ "TARGET_FP"
+ "sub%-%)%& $f31,%R1,%0"
+ [(set_attr "type" "fadd")
+ (set_attr "trap" "yes")])
+
+(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f")
(plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
(match_operand:SF 2 "reg_or_fp0_operand" "fG")))]