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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2020-09-14 09:03:08 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2020-09-15 11:25:09 +0100 |
| commit | 80297f897758f59071968ddff2a04a8d11481117 (patch) | |
| tree | 985ae7b5d0f9d7aaa8ea76a34b4fecc943d957d6 | |
| parent | ecc3135a4a264b66c163ef32e815a99746b81800 (diff) | |
| download | gcc-80297f897758f59071968ddff2a04a8d11481117.zip gcc-80297f897758f59071968ddff2a04a8d11481117.tar.gz gcc-80297f897758f59071968ddff2a04a8d11481117.tar.bz2 | |
arm: Fix testisms introduced with fix for pr target/95646
This patch changes the test to use the effective-target machinery disables the
error message "ARMv8-M Security Extensions incompatible with selected FPU" when
-mfloat-abi=soft.
Further changes 'asm' to '__asm__' to avoid failures with '-std=' options.
gcc/ChangeLog:
2020-07-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.c (arm_options_perform_arch_sanity_checks): Do not
check +D32 for CMSE if -mfloat-abi=soft
gcc/testsuite/ChangeLog:
2020-07-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/arm/pr95646.c: Fix testism.
| -rw-r--r-- | gcc/config/arm/arm.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr95646.c | 11 |
2 files changed, 5 insertions, 8 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index e37cd6f..7d9503c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3820,7 +3820,7 @@ arm_options_perform_arch_sanity_checks (void) /* We don't clear D16-D31 VFP registers for cmse_nonsecure_call functions and ARMv8-M Baseline and Mainline do not allow such configuration. */ - if (use_cmse && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM) + if (use_cmse && TARGET_HARD_FLOAT && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM) error ("ARMv8-M Security Extensions incompatible with selected FPU"); diff --git a/gcc/testsuite/gcc.target/arm/pr95646.c b/gcc/testsuite/gcc.target/arm/pr95646.c index 12d06a0..cde1b2d 100644 --- a/gcc/testsuite/gcc.target/arm/pr95646.c +++ b/gcc/testsuite/gcc.target/arm/pr95646.c @@ -1,10 +1,7 @@ /* { dg-do compile } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv8-m.base" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m23" } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mfpu=*" } { } } */ -/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */ -/* { dg-options "-mcpu=cortex-m23 -mcmse" } */ -/* { dg-additional-options "-Os" } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-add-options arm_arch_v8m_base } */ +/* { dg-additional-options "-mcmse -Os" } */ /* { dg-final { check-function-bodies "**" "" } } */ int __attribute__ ((cmse_nonsecure_entry)) @@ -27,6 +24,6 @@ foo (void) int __attribute__ ((cmse_nonsecure_entry)) bar (void) { - asm ("": : : "r9"); + __asm__ ("" : : : "r9"); return 1; } |