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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-09-11 11:33:59 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-09-11 15:33:05 +0800 |
| commit | 7f9083ffe262cb14c49d042fc6363514badea6cb (patch) | |
| tree | e44513f0e46f3fb60070554c6e718c466958e3f6 | |
| parent | d05aac047e0643d5c32b706c4c3b12e13f35e19a (diff) | |
| download | gcc-7f9083ffe262cb14c49d042fc6363514badea6cb.zip gcc-7f9083ffe262cb14c49d042fc6363514badea6cb.tar.gz gcc-7f9083ffe262cb14c49d042fc6363514badea6cb.tar.bz2 | |
RISC-V: Use dominance analysis in global vsetvl elimination
I found that it's more reasonable to use existing dominance analysis.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn):
Use dominance analysis.
(pass_vsetvl::init): Ditto.
(pass_vsetvl::done): Ditto.
| -rw-r--r-- | gcc/config/riscv/riscv-vsetvl.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 134b977..f81361c 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -4054,7 +4054,7 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const } /* Step1: Reshape the VL/VTYPE status to make sure everything compatible. */ - hash_set<basic_block> pred_cfg_bbs = get_all_predecessors (cfg_bb); + auto_vec<basic_block> pred_cfg_bbs = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb); FOR_EACH_EDGE (e, ei, cfg_bb->preds) { sbitmap avout = m_vector_manager->vector_avout[e->src->index]; @@ -4243,6 +4243,7 @@ pass_vsetvl::init (void) { /* Initialization of RTL_SSA. */ calculate_dominance_info (CDI_DOMINATORS); + calculate_dominance_info (CDI_POST_DOMINATORS); df_analyze (); crtl->ssa = new function_info (cfun); } @@ -4264,6 +4265,7 @@ pass_vsetvl::done (void) { /* Finalization of RTL_SSA. */ free_dominance_info (CDI_DOMINATORS); + free_dominance_info (CDI_POST_DOMINATORS); if (crtl->ssa->perform_pending_updates ()) cleanup_cfg (0); delete crtl->ssa; |