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author | GCC Administrator <gccadmin@gcc.gnu.org> | 2023-05-21 00:16:29 +0000 |
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committer | GCC Administrator <gccadmin@gcc.gnu.org> | 2023-05-21 00:16:29 +0000 |
commit | 7f6e0816f0f5b1e59d05fc96364dec97011f1295 (patch) | |
tree | 4b3e471eb32014a72497345bea2e06d7d5c9a482 | |
parent | b1f399cf6c804bcf6ff14bc4b217ef0b5ca1be11 (diff) | |
download | gcc-7f6e0816f0f5b1e59d05fc96364dec97011f1295.zip gcc-7f6e0816f0f5b1e59d05fc96364dec97011f1295.tar.gz gcc-7f6e0816f0f5b1e59d05fc96364dec97011f1295.tar.bz2 |
Daily bump.
-rw-r--r-- | gcc/ChangeLog | 78 | ||||
-rw-r--r-- | gcc/DATESTAMP | 2 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 20 |
3 files changed, 99 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fb22ceb..68c2664 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,81 @@ +2023-05-20 Gerald Pfeifer <gerald@pfeifer.com> + + * doc/install.texi (Specific): Remove de facto empty alpha*-*-* + section. + +2023-05-20 Pan Li <pan2.li@intel.com> + + * mode-switching.cc (entity_map): Initialize the array to zero. + (bb_info): Ditto. + +2023-05-20 Triffid Hunter <triffid.hunter@gmail.com> + + PR target/105753 + * config/avr/avr.md (divmodpsi, udivmodpsi, divmodsi, udivmodsi): + Remove superfluous "parallel" in insn pattern. + ([u]divmod<mode>4): Tidy code. Use gcc_unreachable() instead of + printing error text to assembly. + +2023-05-20 Andrew Pinski <apinski@marvell.com> + + * expr.cc (fold_single_bit_test): Rename to ... + (expand_single_bit_test): This and expand directly. + (do_store_flag): Update for the rename function. + +2023-05-20 Andrew Pinski <apinski@marvell.com> + + * expr.cc (fold_single_bit_test): Use BIT_FIELD_REF + instead of shift/and. + +2023-05-20 Andrew Pinski <apinski@marvell.com> + + * expr.cc (fold_single_bit_test): Add an assert + and simplify based on code being NE_EXPR or EQ_EXPR. + +2023-05-20 Andrew Pinski <apinski@marvell.com> + + * expr.cc (fold_single_bit_test): Take inner and bitnum + instead of arg0 and arg1. Update the code. + (do_store_flag): Don't create a tree when calling + fold_single_bit_test instead just call it with the bitnum + and the inner tree. + +2023-05-20 Andrew Pinski <apinski@marvell.com> + + * expr.cc (fold_single_bit_test): Use get_def_for_expr + instead of checking the inner's code. + +2023-05-20 Andrew Pinski <apinski@marvell.com> + + * expr.cc (fold_single_bit_test_into_sign_test): Inline into ... + (fold_single_bit_test): This and simplify. + +2023-05-20 Andrew Pinski <apinski@marvell.com> + + * fold-const.cc (fold_single_bit_test_into_sign_test): Move to + expr.cc. + (fold_single_bit_test): Likewise. + * expr.cc (fold_single_bit_test_into_sign_test): Move from fold-const.cc + (fold_single_bit_test): Likewise and make static. + * fold-const.h (fold_single_bit_test): Remove declaration. + +2023-05-20 Die Li <lidie@eswincomputing.com> + + * config/riscv/riscv.cc (riscv_expand_conditional_move): Fix mode + checking. + +2023-05-20 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> + + * config/riscv/bitmanip.md (branch<X:mode>_bext): New split pattern. + +2023-05-20 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> + + PR target/106888 + * config/riscv/bitmanip.md + (<bitmanip_optab>disi2): Match with any_extend. + (<bitmanip_optab>disi2_sext): New pattern to match + with sign extend using an ANDI instruction. + 2023-05-19 Nathan Sidwell <nathan@acm.org> PR other/99451 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 3113e73..7b10b7b 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20230520 +20230521 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ef6ca54..4dc720b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,23 @@ +2023-05-20 Triffid Hunter <triffid.hunter@gmail.com> + + PR target/105753 + * gcc.target/avr/torture/pr105753.c: New test. + +2023-05-20 Die Li <lidie@eswincomputing.com> + + * gcc.target/riscv/xtheadcondmov-indirect-rv32.c: New test. + * gcc.target/riscv/xtheadcondmov-indirect-rv64.c: New test. + +2023-05-20 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> + + * gcc.target/riscv/zbs-bext-02.c: New test. + +2023-05-20 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> + + PR target/106888 + * gcc.target/riscv/pr106888.c: New test. + * gcc.target/riscv/zbbw.c: Check for ANDI. + 2023-05-19 Patrick Palka <ppalka@redhat.com> PR c++/97340 |