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| author | Kirill Yukhin <kirill.yukhin@intel.com> | 2015-04-09 21:37:28 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2015-04-09 21:37:28 +0000 |
| commit | 7f664e31fffc893ab9ef75d08a3fe2dbca21c9fc (patch) | |
| tree | 648330173e6cae8bdec8010c6d1e42c4eb394d3e | |
| parent | febf07f50e449c11c5e809b097dfefe38eb9a639 (diff) | |
| download | gcc-7f664e31fffc893ab9ef75d08a3fe2dbca21c9fc.zip gcc-7f664e31fffc893ab9ef75d08a3fe2dbca21c9fc.tar.gz gcc-7f664e31fffc893ab9ef75d08a3fe2dbca21c9fc.tar.bz2 | |
re PR target/65671 (Assembly failure (invalid register operand) with -O3 -mavx512vl)
PR target/65671
gcc/
* config/i386/sse.md: Generate vextract32x4 if AVX-512DQ
is disabled.
gcc/testsuite/
* gcc.target/i386/pr65671.c: New.
From-SVN: r221963
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 11 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr65671.c | 15 |
4 files changed, 34 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 133007f..43a341e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-04-09 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/65671 + * config/i386/sse.md: Generate vextract32x4 if AVX-512DQ + is disabled. + 2015-04-09 Gerald Pfeifer <gerald@pfeifer.com> * doc/contrib.texi (Contributors): Add John Marino. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 490fd6b..6d3b54a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -7015,10 +7015,15 @@ (vec_select:<ssehalfvecmode> (match_operand:VI8F_256 1 "register_operand" "v,v") (parallel [(const_int 2) (const_int 3)])))] - "TARGET_AVX" + "TARGET_AVX && <mask_avx512vl_condition> && <mask_avx512dq_condition>" { - if (TARGET_AVX512DQ && TARGET_AVX512VL) - return "vextract<shuffletype>64x2\t{$0x1, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x1}"; + if (TARGET_AVX512VL) + { + if (TARGET_AVX512DQ) + return "vextract<shuffletype>64x2\t{$0x1, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x1}"; + else + return "vextract<shuffletype>32x4\t{$0x1, %1, %0|%0, %1, 0x1}"; + } else return "vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}"; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4be085d..7130536 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-04-09 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/65671 + * gcc.target/i386/pr65671.c: New. + 2015-04-09 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/65709 diff --git a/gcc/testsuite/gcc.target/i386/pr65671.c b/gcc/testsuite/gcc.target/i386/pr65671.c new file mode 100644 index 0000000..8e5d00d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr65671.c @@ -0,0 +1,15 @@ +/* PR target/65671 */ +/* { dg-do assemble } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mavx512vl -ffixed-ymm16" } */ + +#include <x86intrin.h> + +register __m256d a asm ("ymm16"); +__m128d b; + +void +foo () +{ + b = _mm256_extractf128_pd (a, 1); +} |