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authorTsukasa OI <research_trasio@irq.a4lg.com>2023-09-19 02:10:31 +0000
committerTsukasa OI <research_trasio@irq.a4lg.com>2023-09-19 02:46:10 +0000
commit7f4fc87086b5ad57edaaf628ba6cb92649d14453 (patch)
tree945e551c066f487a90add6645e228b7a70153fac
parentf45cca26263c3563e9db15e0ba64d4a114316808 (diff)
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RISC-V: Fix typos on comments (SVE -> RVV)
We have the 'V' extension (RVV), not SVE from AArch64. gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (builtin_decl, expand_builtin): Replace SVE with RVV.
-rw-r--r--gcc/config/riscv/riscv-vector-builtins.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 5318651..5d4dc26 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4172,7 +4172,7 @@ builtin_decl (unsigned int code, bool)
return (*registered_functions)[code]->decl;
}
-/* Attempt to fold STMT, given that it's a call to the SVE function
+/* Attempt to fold STMT, given that it's a call to the RVV function
with subcode CODE. Return the new statement on success and null
on failure. Insert any other new statements at GSI. */
gimple *
@@ -4192,7 +4192,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
}
-/* Perform any semantic checks needed for a call to the SVE function
+/* Perform any semantic checks needed for a call to the RVV function
with subcode CODE, such as testing for integer constant expressions.
The call occurs at location LOCATION and has NARGS arguments,
given by ARGS. FNDECL is the original function decl, before