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authorCatherine Moore <clm@codesourcery.com>2015-10-28 14:09:09 -0400
committerCatherine Moore <clm@gcc.gnu.org>2015-10-28 14:09:09 -0400
commit7bc2eabe25d3b40fdb8e2e26508dd89f47906c3c (patch)
tree23746ca48757180579eac917f4453a590571cce2
parentf64ba10b91544a8a9ad304e6be1cac8809513faa (diff)
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oddspreg-3.c: Disable for MIPS16.
2015-10-28 Catherine Moore <clm@codesourcery.com> * gcc.target/mips/oddspreg-3.c: Disable for MIPS16. * gcc.target/mips/oddspreg-6.c: Likewise. * gcc.target/mips/oddspreg-1.c: Likewise. * gcc.target/mips/oddspreg-2.c: Likewise. From-SVN: r229496
-rw-r--r--gcc/testsuite/ChangeLog7
-rw-r--r--gcc/testsuite/gcc.target/mips/oddspreg-1.c2
-rw-r--r--gcc/testsuite/gcc.target/mips/oddspreg-2.c2
-rw-r--r--gcc/testsuite/gcc.target/mips/oddspreg-3.c2
-rw-r--r--gcc/testsuite/gcc.target/mips/oddspreg-6.c2
5 files changed, 11 insertions, 4 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index cc04c43..5ca99b0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2015-10-28 Catherine Moore <clm@codesourcery.com>
+
+ * gcc.target/mips/oddspreg-3.c: Disable for MIPS16.
+ * gcc.target/mips/oddspreg-6.c: Likewise.
+ * gcc.target/mips/oddspreg-1.c: Likewise.
+ * gcc.target/mips/oddspreg-2.c: Likewise.
+
2015-10-05 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR target/67839
diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-1.c b/gcc/testsuite/gcc.target/mips/oddspreg-1.c
index a9c6957..d44563d 100644
--- a/gcc/testsuite/gcc.target/mips/oddspreg-1.c
+++ b/gcc/testsuite/gcc.target/mips/oddspreg-1.c
@@ -5,7 +5,7 @@
#error "Incorrect number of single-precision registers reported"
#endif
-void
+NOMIPS16 void
foo ()
{
register float foo asm ("$f1");
diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-2.c b/gcc/testsuite/gcc.target/mips/oddspreg-2.c
index e2e0a26..efeb0af 100644
--- a/gcc/testsuite/gcc.target/mips/oddspreg-2.c
+++ b/gcc/testsuite/gcc.target/mips/oddspreg-2.c
@@ -2,7 +2,7 @@
/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" } } */
/* { dg-options "-mabi=32 -mno-odd-spreg -mhard-float" } */
-void
+NOMIPS16 void
foo ()
{
register float foo asm ("$f1"); /* { dg-error "isn't suitable for" } */
diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-3.c b/gcc/testsuite/gcc.target/mips/oddspreg-3.c
index f287eb6..8a0d85c 100644
--- a/gcc/testsuite/gcc.target/mips/oddspreg-3.c
+++ b/gcc/testsuite/gcc.target/mips/oddspreg-3.c
@@ -2,7 +2,7 @@
/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" } } */
/* { dg-options "-mabi=32 -mfp32 -march=loongson3a -mhard-float" } */
-void
+NOMIPS16 void
foo ()
{
register float foo asm ("$f1"); /* { dg-error "isn't suitable for" } */
diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-6.c b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
index 955dea901..eb376c6 100644
--- a/gcc/testsuite/gcc.target/mips/oddspreg-6.c
+++ b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
@@ -2,7 +2,7 @@
/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" } } */
/* { dg-options "-mabi=32 -mfpxx -mhard-float" } */
-void
+NOMIPS16 void
foo ()
{
register float foo asm ("$f1"); /* { dg-error "isn't suitable for" } */