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| author | Andrew Stubbs <ams@codesourcery.com> | 2019-12-13 16:37:17 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@gcc.gnu.org> | 2019-12-13 16:37:17 +0000 |
| commit | 7b945b19ad7cebebbaaf4eec44a7a572233ab91b (patch) | |
| tree | 161a3884f056e764c37a7aa3c9e9b7f681972ae3 | |
| parent | e44deb433b5c4eac6caeae284e9eebbb3760531c (diff) | |
| download | gcc-7b945b19ad7cebebbaaf4eec44a7a572233ab91b.zip gcc-7b945b19ad7cebebbaaf4eec44a7a572233ab91b.tar.gz gcc-7b945b19ad7cebebbaaf4eec44a7a572233ab91b.tar.bz2 | |
Sub-dword vector multiply for amdgcn
2019-12-13 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (mulv64si3<exec>): Rename to ...
(mul<mode>3<exec>): ... this, and implement sub-dword patterns.
(mulv64si3_dup<exec>): Rename to ...
(mul<mode>3_dup<exec>): ... this, and implement sub-dword patterns.
From-SVN: r279374
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/gcn/gcn-valu.md | 22 |
2 files changed, 18 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c40d936..88482c6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-12-13 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (mulv64si3<exec>): Rename to ... + (mul<mode>3<exec>): ... this, and implement sub-dword patterns. + (mulv64si3_dup<exec>): Rename to ... + (mul<mode>3_dup<exec>): ... this, and implement sub-dword patterns. + 2019-12-13 Jan Hubicka <hubicka@ucw.cz> * ipa-utils.c (ipa_merge_profiles): Improve dumping; merge common diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index e1b3c71..4260446 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -1740,22 +1740,22 @@ [(set_attr "type" "vop3a") (set_attr "length" "8")]) -(define_insn "mulv64si3<exec>" - [(set (match_operand:V64SI 0 "register_operand" "= v") - (mult:V64SI - (match_operand:V64SI 1 "gcn_alu_operand" "%vSvA") - (match_operand:V64SI 2 "gcn_alu_operand" " vSvA")))] +(define_insn "mul<mode>3<exec>" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v") + (mult:VEC_ALL1REG_INT_MODE + (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "%vSvA") + (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_operand" " vSvA")))] "" "v_mul_lo_u32\t%0, %1, %2" [(set_attr "type" "vop3a") (set_attr "length" "8")]) -(define_insn "mulv64si3_dup<exec>" - [(set (match_operand:V64SI 0 "register_operand" "= v") - (mult:V64SI - (match_operand:V64SI 1 "gcn_alu_operand" "%vSvA") - (vec_duplicate:V64SI - (match_operand:SI 2 "gcn_alu_operand" " SvA"))))] +(define_insn "mul<mode>3_dup<exec>" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v") + (mult:VEC_ALL1REG_INT_MODE + (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "%vSvA") + (vec_duplicate:VEC_ALL1REG_INT_MODE + (match_operand:<SCALAR_MODE> 2 "gcn_alu_operand" " SvA"))))] "" "v_mul_lo_u32\t%0, %1, %2" [(set_attr "type" "vop3a") |