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author | GCC Administrator <gccadmin@gcc.gnu.org> | 2022-12-28 00:17:27 +0000 |
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committer | GCC Administrator <gccadmin@gcc.gnu.org> | 2022-12-28 00:17:27 +0000 |
commit | 7b885ecc05fef0e7437ace59254336f8e8d9ebe6 (patch) | |
tree | 9d24ab2b8197b664488b005f6f3faddc2603700c | |
parent | 103f963e5cf6e7fe80395efc5fcede351420e25d (diff) | |
download | gcc-7b885ecc05fef0e7437ace59254336f8e8d9ebe6.zip gcc-7b885ecc05fef0e7437ace59254336f8e8d9ebe6.tar.gz gcc-7b885ecc05fef0e7437ace59254336f8e8d9ebe6.tar.bz2 |
Daily bump.
-rw-r--r-- | gcc/ChangeLog | 88 | ||||
-rw-r--r-- | gcc/DATESTAMP | 2 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 20 |
3 files changed, 109 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e429553..f670edf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,91 @@ +2022-12-27 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/riscv.md: Add missing modes to last patch.t + +2022-12-27 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> + + PR target/95632 + PR target/106602 + * config/riscv/riscv.md: New pattern to simulate complex + const_int loads. + +2022-12-27 Christoph Müllner <christoph.muellner@vrull.eu> + + * config/riscv/riscv.cc (riscv_next_saved_reg): New function. + (riscv_is_eh_return_data_register): New function. + (riscv_for_each_saved_reg): Restructure loop. + +2022-12-27 Christoph Müllner <christoph.muellner@vrull.eu> + + * config/riscv/riscv.md: Sync comments with code. + +2022-12-27 jinma <jinma@linux.alibaba.com> + + * common/config/riscv/riscv-common.cc: + +2022-12-27 Jonathan Yong <10walls@gmail.com> + + * configure.ac: use grep -i for case insensitive test. + * configure: Regenerate. + +2022-12-27 Max Filippov <jcmvbkbc@gmail.com> + + * config/xtensa/xtensa.md (unspec): Extract UNSPEC_* constants + into this enum. + (unspecv): Extract UNSPECV_* constants into this enum. + +2022-12-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (set_frame_ptr): Fix to reflect + TARGET_DENSITY. + +2022-12-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.h (GP_RETURN, GP_RETURN_REG_COUNT): + Change to GP_RETURN_FIRST and GP_RETURN_LAST, respectively. + * config/xtensa/xtensa.cc (xtensa_function_value, + xtensa_libcall_value, xtensa_function_value_regno_p): Ditto. + +2022-12-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_expand_prologue): Modify to + exit the inspection loops as soon as the necessity of stack + pointer is found. + +2022-12-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/elf.h: Tabify, and trim trailing spaces. + * config/xtensa/linux.h: Likewise. + * config/xtensa/uclinux.h: Likewise. + * config/xtensa/xtensa-dynconfig.c: Likewise. + * config/xtensa/xtensa.cc: Likewise. + * config/xtensa/xtensa.h: Likewise. + * config/xtensa/xtensa.md: Likewise. + +2022-12-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vsetvl.cc + (pass_vsetvl::compute_global_backward_infos): Change to visit CFG. + (pass_vsetvl::prune_expressions): Ditto. + +2022-12-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vsetvl.cc (change_insn): Remove pp_print. + (avl_info::avl_info): Add copy function. + (vector_insn_info::dump): Remove pp_print. + * config/riscv/riscv-vsetvl.h: Add copy function. + +2022-12-27 Kewen Lin <linkw@linux.ibm.com> + + PR target/106680 + * common/config/rs6000/rs6000-common.cc (rs6000_handle_option): Remove + the adjustment for option powerpc64 in -m64 handling, and remove the + whole -m32 handling. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): When no + explicit powerpc64 option is provided, enable it for -m64. For 32 bit + and OS_MISSING_POWERPC64, disable powerpc64 if it's enabled but not + specified explicitly. + 2022-12-26 liuhongt <hongtao.liu@intel.com> PR target/55522 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 154fbb1..e65d79f 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20221227 +20221228 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6ce8119..7dd0a49 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,23 @@ +2022-12-27 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> + + PR target/95632 + PR target/106602 + * gcc.target/riscv/pr95632.c: New test. + * gcc.target/riscv/pr106602.c: New test. + +2022-12-27 Kito Cheng <kito.cheng@sifive.com> + + * gcc.target/riscv/rvv/vsetvl/riscv_vector.h: New. + +2022-12-27 Kewen Lin <linkw@linux.ibm.com> + Iain Sandoe <iain@sandoe.co.uk> + + PR target/106680 + * gcc.target/powerpc/pr106680-1.c: New test. + * gcc.target/powerpc/pr106680-2.c: New test. + * gcc.target/powerpc/pr106680-3.c: New test. + * gcc.target/powerpc/pr106680-4.c: New test. + 2022-12-26 David Edelsohn <dje.gcc@gmail.com> * gcc.dg/analyzer/fd-accept.c: Skip. |