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| author | Chung-Ju Wu <jasonwucj@gmail.com> | 2018-04-04 09:19:39 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gcc.gnu.org> | 2018-04-04 09:19:39 +0000 |
| commit | 76dc9cb5971da64985103f737c5d163ef97d2d6b (patch) | |
| tree | a4f4b007429b9f52aadccb842582f43d7e396581 | |
| parent | 6e9ca9328ae625ad366d6a1043f2b8df58b56cb6 (diff) | |
| download | gcc-76dc9cb5971da64985103f737c5d163ef97d2d6b.zip gcc-76dc9cb5971da64985103f737c5d163ef97d2d6b.tar.gz gcc-76dc9cb5971da64985103f737c5d163ef97d2d6b.tar.bz2 | |
[NDS32] Merge movqi and movhi patterns.
gcc/
* config/nds32/nds32.md (movqi, movhi): Merge into mov<mode>.
From-SVN: r259071
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32.md | 25 |
2 files changed, 16 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 651523f..3555f35 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,8 @@ 2018-04-04 Chung-Ju Wu <jasonwucj@gmail.com> + + * config/nds32/nds32.md (movqi, movhi): Merge into mov<mode>. + +2018-04-04 Chung-Ju Wu <jasonwucj@gmail.com> Kito Cheng <kito.cheng@gmail.com> * config/nds32/nds32-md-auxiliary.c (nds32_inverse_cond_code, diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index 662be73..9a12598 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -83,26 +83,25 @@ ;; For QImode and HImode, the immediate value can be fit in imm20s. ;; So there is no need to split rtx for QI and HI patterns. -(define_expand "movqi" - [(set (match_operand:QI 0 "general_operand" "") - (match_operand:QI 1 "general_operand" ""))] +(define_expand "mov<mode>" + [(set (match_operand:QIHI 0 "general_operand" "") + (match_operand:QIHI 1 "general_operand" ""))] "" { /* Need to force register if mem <- !reg. */ if (MEM_P (operands[0]) && !REG_P (operands[1])) - operands[1] = force_reg (QImode, operands[1]); -}) + operands[1] = force_reg (<MODE>mode, operands[1]); -(define_expand "movhi" - [(set (match_operand:HI 0 "general_operand" "") - (match_operand:HI 1 "general_operand" ""))] - "" -{ - /* Need to force register if mem <- !reg. */ - if (MEM_P (operands[0]) && !REG_P (operands[1])) - operands[1] = force_reg (HImode, operands[1]); + if (MEM_P (operands[1]) && optimize > 0) + { + rtx reg = gen_reg_rtx (SImode); + + emit_insn (gen_zero_extend<mode>si2 (reg, operands[1])); + operands[1] = gen_lowpart (<MODE>mode, reg); + } }) + (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] |