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| author | Pan Li <pan2.li@intel.com> | 2023-08-02 15:59:24 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-08 22:21:40 +0800 |
| commit | 733e8b48cba745d80ca2d52c1e4f47d1075e30d6 (patch) | |
| tree | ebf14c6bf4af0954a990633d24217e605584e65d | |
| parent | d9dc70cc65becca95a5f2e43bf8bd2d452b5796f (diff) | |
| download | gcc-733e8b48cba745d80ca2d52c1e4f47d1075e30d6.zip gcc-733e8b48cba745d80ca2d52c1e4f47d1075e30d6.tar.gz gcc-733e8b48cba745d80ca2d52c1e4f47d1075e30d6.tar.bz2 | |
RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding
This patch would like to enhance the vfsub/vfrsub rounding API test for
below 2 purposes.
* The non-rm API has no frm related insn generated.
* The rm API has the frm backup/restore/set insn generated.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-rsub.c: Enhance
cases.
* gcc.target/riscv/rvv/base/float-point-single-sub.c: Ditto.
Signed-off-by: Pan Li <pan2.li@intel.com>
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c | 16 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c | 16 |
2 files changed, 30 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c index 1d770ad..86c56b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c @@ -16,4 +16,18 @@ test_vfrsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, return __riscv_vfrsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl); } -/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +vfloat32m1_t +test_vfrsub_vf_f32m1 (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfrsub_vf_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfrsub_vf_f32m1_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfrsub_vf_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c index 34ed03a..8075dce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c @@ -27,4 +27,18 @@ test_vfsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, return __riscv_vfsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl); } -/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ +vfloat32m1_t +test_riscv_vfsub_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfsub_vv_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfsub_vv_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ |