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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-12-19 19:40:48 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-12-19 21:14:22 +0800 |
| commit | 71bc7c6fa116dec13ca0c636c2755d26f3341b33 (patch) | |
| tree | 291d7ea29b367963d28e2b17a91d41b7036116f7 | |
| parent | afd49e663258061a10f0f2c4a8f8aa2bf97bee42 (diff) | |
| download | gcc-71bc7c6fa116dec13ca0c636c2755d26f3341b33.zip gcc-71bc7c6fa116dec13ca0c636c2755d26f3341b33.tar.gz gcc-71bc7c6fa116dec13ca0c636c2755d26f3341b33.tar.bz2 | |
RISC-V: Fix FAIL of bb-slp-cond-1.c for RVV
Due to recent VLSmode changes (Change for fixing ICE and run-time FAIL).
The dump check is same as ARM SVE now. So adapt test for RISC-V.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-cond-1.c: Adapt for RISC-V.
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c b/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c index 4089eb5..8faf6b6 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c @@ -47,6 +47,6 @@ int main () } /* { dg-final { scan-tree-dump {(no need for alias check [^\n]* when VF is 1|no alias between [^\n]* when [^\n]* is outside \(-16, 16\))} "vect" { target vect_element_align } } } */ -/* { dg-final { scan-tree-dump-times "loop vectorized" 1 "vect" { target { vect_element_align && { ! { amdgcn-*-* riscv*-*-* } } } } } } */ -/* { dg-final { scan-tree-dump-times "loop vectorized" 2 "vect" { target { amdgcn-*-* riscv*-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "loop vectorized" 1 "vect" { target { vect_element_align && { ! { amdgcn-*-* } } } } } } */ +/* { dg-final { scan-tree-dump-times "loop vectorized" 2 "vect" { target { amdgcn-*-* } } } } */ |