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authorSteve Ellcey <sellcey@imgtec.com>2015-03-03 00:07:19 +0000
committerSteve Ellcey <sje@gcc.gnu.org>2015-03-03 00:07:19 +0000
commit7096a06885f16413b4710a58f15f8f25de29bb00 (patch)
treec2905d68998e49745c2cdb565fcda6057db24632
parent29e27c0bf3c42ae67fe42a556056504b9d5cabad (diff)
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re PR target/58158 (ICE with conditional moves on GPRs with a floating point conditional on mipsel with loongson2f)
2015-03-02 Steve Ellcey <sellcey@imgtec.com> PR target/58158 * config/mips/mips.md (mov<mode>cc): Change ISA_HAS_SEL check to !ISA_HAS_FP_CONDMOVE. From-SVN: r221128
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/config/mips/mips.md3
2 files changed, 8 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index acfb16c..09ebb7e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2015-03-02 Steve Ellcey <sellcey@imgtec.com>
+
+ PR target/58158
+ * config/mips/mips.md (mov<mode>cc): Change ISA_HAS_SEL check to
+ !ISA_HAS_FP_CONDMOVE.
+
2015-03-02 Aldy Hernandez <aldyh@redhat.com>
* config/i386/i386.md (*udivmod<mode>4_pow2): Remove
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 2fb2786..3672c0b 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -7150,7 +7150,8 @@
(match_operand:GPR 3 "reg_or_0_operand")))]
"ISA_HAS_CONDMOVE || ISA_HAS_SEL"
{
- if (ISA_HAS_SEL && !INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0))))
+ if (!ISA_HAS_FP_CONDMOVE
+ && !INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0))))
FAIL;
mips_expand_conditional_move (operands);