This is being installed only to get it into the repository to help with the revert...

        This is being installed only to get it into the repository to help
        with the revert, resubmit & review process for the massive rs6000.md
        changes.
        * rs6000.md (andsi3_internal1 splitter): Don't split if using the
        rlwinm instruction.
        (anddi3_internal1): Ditto.
        (andsi3_internal{2,3}): Correct some insn lengths.
        (anddi3*): Restore missing TARGET_POWERPC64, and don't emit old
        mnemonics.

From-SVN: r25099

2 files changed, 34 insertions, 20 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fa39496..6883675 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+1999-02-08  Michael Meissner  <meissner@cygnus.com>
+
+	This is being installed only to get it into the repository to help
+	with the revert, resubmit & review process for the massive rs6000.md
+	changes.
+        * rs6000.md (andsi3_internal1 splitter): Don't split if using the
+        rlwinm instruction.
+        (anddi3_internal1): Ditto.
+        (andsi3_internal{2,3}): Correct some insn lengths.
+        (anddi3*): Restore missing TARGET_POWERPC64, and don't emit old
+        mnemonics.
+
 Mon Feb  8 21:31:06 1999  Richard Henderson  <rth@cygnus.com>
 
 	* loop.c (reg_single_usage): New file-scope variable ...
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4dc9686..b73aa35 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2570,7 +2570,7 @@
 	(and:SI (match_operand:SI 1 "gpc_reg_operand" "")
 		(match_operand:SI 2 "const_int_operand" "")))
    (clobber (scratch:CC))]
-  "reload_completed"
+  "reload_completed && !mask_constant (INTVAL (operands[2]))"
   [(set (match_dup 0)
 	(match_dup 2))
    (parallel [(set (match_dup 0)
@@ -2603,7 +2603,7 @@
    #
    #"
   [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")
-   (set_attr "length" "4,4,4,4,8,12,12,8,16,16")])
+   (set_attr "length" "4,4,4,4,8,8,8,8,12,12")])
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
@@ -2643,7 +2643,8 @@
    #
    #
    #"
-  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")])
+  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")
+   (set_attr "length" "4,4,4,4,8,8,8,8,12,12")])
 
 (define_split
   [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
@@ -7480,7 +7481,7 @@
 		   (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
 			   (match_operand:DI 2 "and_operand" "?r,L,K,J")))
 	      (clobber (match_scratch:CC 3 "=X,X,x,x"))])]
-  ""
+  "TARGET_POWERPC64"
   "")
 
 ;; If cr0 isn't available, and we want to do an andi, load the register into
@@ -7491,12 +7492,12 @@
 	(and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
 		(match_operand:DI 2 "and_operand" "?r,L,K,J,K,J")))
    (clobber (match_operand:CC 3 "scratch_operand" "=X,X,x,x,X,X"))]
-  ""
+  "TARGET_POWERPC64"
   "@
    and %0,%1,%2
    {rlinm|rlwinm} %0,%1,0,%m2,%M2
-   {andil.|andi.} %0,%1,%b2
-   {andiu.|andis.} %0,%1,%u2
+   andil %0,%1,%b2
+   andis. %0,%1,%u2
    #
    #"
   [(set_attr "length" "4,4,4,4,8,8")])
@@ -7506,7 +7507,7 @@
 	(and:DI (match_operand:DI 1 "gpc_reg_operand" "")
 		(match_operand:DI 2 "const_int_operand" "")))
    (clobber (scratch:CC))]
-  "reload_completed"
+  "TARGET_POWERPC64 && reload_completed && !mask_constant (INTVAL (operands[2]))"
   [(set (match_dup 0)
 	(match_dup 2))
    (parallel [(set (match_dup 0)
@@ -7526,12 +7527,12 @@
 		    (const_int 0)))
    (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,&r,&r"))
    (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))]
-  ""
+  "TARGET_POWERPC64"
   "@
    and. %3,%1,%2
-   {andil.|andi.} %3,%1,%b2
-   {andiu.|andis.} %3,%1,%u2
-   {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
+   andi. %3,%1,%b2
+   andis. %3,%1,%u2
+   rldic%B2. %3,%1,0,%S2
    #
    #
    #
@@ -7539,7 +7540,7 @@
    #
    #"
   [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")
-   (set_attr "length" "4,4,4,4,8,12,12,8,16,16")])
+   (set_attr "length" "4,4,4,4,8,8,8,8,12,12")])
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
@@ -7548,7 +7549,7 @@
 		    (const_int 0)))
    (clobber (match_scratch:DI 3 ""))
    (clobber (match_scratch:CC 4 ""))]
-  "reload_completed"
+  "TARGET_POWERPC64 && reload_completed"
   [(parallel [(set (match_dup 3)
 		   (and:DI (match_dup 1)
 			   (match_dup 2)))
@@ -7567,19 +7568,20 @@
 	(and:DI (match_dup 1)
 		(match_dup 2)))
    (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))]
-  ""
+  "TARGET_POWERPC64"
   "@
    and. %0,%1,%2
-   {andil.|andi.} %0,%1,%b2
-   {andiu.|andis.} %0,%1,%u2
-   {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
+   andi. %0,%1,%b2
+   andis. %0,%1,%u2
+   rldic%B2 %0,%1,0,%m2,%M2
    #
    #
    #
    #
    #
    #"
-  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")])
+  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")
+   (set_attr "length" "4,4,4,4,8,8,8,8,12,12")])
 
 (define_split
   [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
@@ -7590,7 +7592,7 @@
 	(and:DI (match_dup 1)
 		(match_dup 2)))
    (clobber (match_scratch:CC 4 ""))]
-  "reload_completed"
+  "TARGET_POWERPC64 && reload_completed"
   [(parallel [(set (match_dup 0)
 		   (and:DI (match_dup 1)
 			   (match_dup 2)))