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| author | H.J. Lu <hjl.tools@gmail.com> | 2021-08-01 09:55:33 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2021-08-01 13:32:55 -0700 |
| commit | 6f0c43e97825ee54e3779afbedcd0def12443001 (patch) | |
| tree | 96c88229bdbe88003206abe51a0803d7d5f99843 | |
| parent | 8dd16447343890091874c9f588a7fea8c840cf77 (diff) | |
| download | gcc-6f0c43e97825ee54e3779afbedcd0def12443001.zip gcc-6f0c43e97825ee54e3779afbedcd0def12443001.tar.gz gcc-6f0c43e97825ee54e3779afbedcd0def12443001.tar.bz2 | |
i386: Improve SImode constant - __builtin_clzll for -mno-lzcnt
Add a zero_extend patten for bsr_rex64_1 and use it to split SImode
constant - __builtin_clzll to avoid unncessary zero_extend.
gcc/
PR target/78103
* config/i386/i386.md (bsr_rex64_1_zext): New.
(combine splitter for constant - clzll): Replace gen_bsr_rex64_1
with gen_bsr_rex64_1_zext.
gcc/testsuite/
PR target/78103
* gcc.target/i386/pr78103-2.c: Also scan incl.
* gcc.target/i386/pr78103-3.c: Scan leal|addl|incl for x32. Also
scan incq.
| -rw-r--r-- | gcc/config/i386/i386.md | 17 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr78103-2.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr78103-3.c | 3 |
3 files changed, 19 insertions, 3 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c9787d7..0c23ddb 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -14796,6 +14796,21 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "DI")]) +(define_insn "bsr_rex64_1_zext" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (minus:SI (const_int 63) + (subreg:SI + (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")) + 0)))) + (clobber (reg:CC FLAGS_REG))] + "!TARGET_LZCNT && TARGET_64BIT" + "bsr{q}\t{%1, %0|%0, %1}" + [(set_attr "type" "alu1") + (set_attr "prefix_0f" "1") + (set_attr "znver1_decode" "vector") + (set_attr "mode" "DI")]) + (define_insn "bsr" [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm") @@ -14907,7 +14922,7 @@ operands[5] = lowpart_subreg (SImode, operands[3], DImode); if (INTVAL (operands[2]) == 63) { - emit_insn (gen_bsr_rex64_1 (operands[3], operands[1])); + emit_insn (gen_bsr_rex64_1_zext (operands[3], operands[1])); emit_move_insn (operands[0], operands[5]); DONE; } diff --git a/gcc/testsuite/gcc.target/i386/pr78103-2.c b/gcc/testsuite/gcc.target/i386/pr78103-2.c index b352338..30f7f98 100644 --- a/gcc/testsuite/gcc.target/i386/pr78103-2.c +++ b/gcc/testsuite/gcc.target/i386/pr78103-2.c @@ -4,7 +4,7 @@ /* { dg-final { scan-assembler-not {\mmovl\M} } } */ /* { dg-final { scan-assembler-not {\mxor[lq]\M} } } */ /* { dg-final { scan-assembler-not {\msubl\M} } } */ -/* { dg-final { scan-assembler {\m(leal|addl)\M} } } */ +/* { dg-final { scan-assembler {\m(leal|addl|incl)\M} } } */ unsigned int foo (unsigned int x) diff --git a/gcc/testsuite/gcc.target/i386/pr78103-3.c b/gcc/testsuite/gcc.target/i386/pr78103-3.c index 49a36ec..b8d8231 100644 --- a/gcc/testsuite/gcc.target/i386/pr78103-3.c +++ b/gcc/testsuite/gcc.target/i386/pr78103-3.c @@ -5,7 +5,8 @@ /* { dg-final { scan-assembler-not {\mmovslq\M} } } */ /* { dg-final { scan-assembler-not {\mxor[lq]\M} } } */ /* { dg-final { scan-assembler-not {\msubq\M} } } */ -/* { dg-final { scan-assembler {\m(leaq|addq)\M} } } */ +/* { dg-final { scan-assembler {\m(leaq|addq|incq)\M} { target { ! x32 } } } } */ +/* { dg-final { scan-assembler {\m(leal|addl|incl)\M} { target x32 } } } */ unsigned long long foo (unsigned int x) |