RISC-V/testsuite: Run target testing over all the usual optimization levels

Use `gcc-dg-runtest' test driver rather than `dg-runtest' to run the RISC-V testsuite as several targets already do. Adjust test options across individual test cases accordingly where required. As some tests want to be run at `-Og', add a suitable optimization variant via ADDITIONAL_TORTURE_OPTIONS, and include the moderately recent `-Oz' variant as well. gcc/testsuite/ * gcc.target/riscv/riscv.exp: Use `gcc-dg-runtest' rather than `dg-runtest'. Add `-Og -g' and `-Oz' variants via ADDITIONAL_TORTURE_OPTIONS. * gcc.target/riscv/arch-1.c: Adjust test options accordingly. * gcc.target/riscv/arch-10.c: Likewise. * gcc.target/riscv/arch-11.c: Likewise. * gcc.target/riscv/arch-12.c: Likewise. * gcc.target/riscv/arch-2.c: Likewise. * gcc.target/riscv/arch-3.c: Likewise. * gcc.target/riscv/arch-4.c: Likewise. * gcc.target/riscv/arch-5.c: Likewise. * gcc.target/riscv/arch-6.c: Likewise. * gcc.target/riscv/arch-7.c: Likewise. * gcc.target/riscv/arch-8.c: Likewise. * gcc.target/riscv/arch-9.c: Likewise. * gcc.target/riscv/attribute-1.c: Likewise. * gcc.target/riscv/attribute-10.c: Likewise. * gcc.target/riscv/attribute-11.c: Likewise. * gcc.target/riscv/attribute-12.c: Likewise. * gcc.target/riscv/attribute-13.c: Likewise. * gcc.target/riscv/attribute-14.c: Likewise. * gcc.target/riscv/attribute-15.c: Likewise. * gcc.target/riscv/attribute-16.c: Likewise. * gcc.target/riscv/attribute-17.c: Likewise. * gcc.target/riscv/attribute-2.c: Likewise. * gcc.target/riscv/attribute-3.c: Likewise. * gcc.target/riscv/attribute-4.c: Likewise. * gcc.target/riscv/attribute-5.c: Likewise. * gcc.target/riscv/attribute-7.c: Likewise. * gcc.target/riscv/attribute-8.c: Likewise. * gcc.target/riscv/attribute-9.c: Likewise. * gcc.target/riscv/interrupt-1.c: Likewise. * gcc.target/riscv/interrupt-2.c: Likewise. * gcc.target/riscv/interrupt-3.c: Likewise. * gcc.target/riscv/interrupt-4.c: Likewise. * gcc.target/riscv/interrupt-conflict-mode.c: Likewise. * gcc.target/riscv/interrupt-debug.c: Likewise. * gcc.target/riscv/interrupt-mmode.c: Likewise. * gcc.target/riscv/interrupt-smode.c: Likewise. * gcc.target/riscv/interrupt-umode.c: Likewise. * gcc.target/riscv/li.c: Likewise. * gcc.target/riscv/load-immediate.c: Likewise. * gcc.target/riscv/losum-overflow.c: Likewise. * gcc.target/riscv/mcpu-6.c: Likewise. * gcc.target/riscv/mcpu-7.c: Likewise. * gcc.target/riscv/pr102957.c: Likewise. * gcc.target/riscv/pr103302.c: Likewise. * gcc.target/riscv/pr104140.c: Likewise. * gcc.target/riscv/pr84660.c: Likewise. * gcc.target/riscv/pr93202.c: Likewise. * gcc.target/riscv/pr93304.c: Likewise. * gcc.target/riscv/pr95252.c: Likewise. * gcc.target/riscv/pr95683.c: Likewise. * gcc.target/riscv/pr98777.c: Likewise. * gcc.target/riscv/pr99702.c: Likewise. * gcc.target/riscv/predef-1.c: Likewise. * gcc.target/riscv/predef-10.c: Likewise. * gcc.target/riscv/predef-11.c: Likewise. * gcc.target/riscv/predef-12.c: Likewise. * gcc.target/riscv/predef-13.c: Likewise. * gcc.target/riscv/predef-14.c: Likewise. * gcc.target/riscv/predef-15.c: Likewise. * gcc.target/riscv/predef-16.c: Likewise. * gcc.target/riscv/predef-2.c: Likewise. * gcc.target/riscv/predef-3.c: Likewise. * gcc.target/riscv/predef-4.c: Likewise. * gcc.target/riscv/predef-5.c: Likewise. * gcc.target/riscv/predef-6.c: Likewise. * gcc.target/riscv/predef-7.c: Likewise. * gcc.target/riscv/predef-8.c: Likewise. * gcc.target/riscv/promote-type-for-libcall.c: Likewise. * gcc.target/riscv/save-restore-1.c: Likewise. * gcc.target/riscv/save-restore-2.c: Likewise. * gcc.target/riscv/save-restore-3.c: Likewise. * gcc.target/riscv/save-restore-4.c: Likewise. * gcc.target/riscv/save-restore-6.c: Likewise. * gcc.target/riscv/save-restore-7.c: Likewise. * gcc.target/riscv/save-restore-8.c: Likewise. * gcc.target/riscv/save-restore-9.c: Likewise. * gcc.target/riscv/shift-and-1.c: Likewise. * gcc.target/riscv/shift-and-2.c: Likewise. * gcc.target/riscv/shift-shift-1.c: Likewise. * gcc.target/riscv/shift-shift-2.c: Likewise. * gcc.target/riscv/shift-shift-3.c: Likewise. * gcc.target/riscv/shift-shift-4.c: Likewise. * gcc.target/riscv/shift-shift-5.c: Likewise. * gcc.target/riscv/shorten-memrefs-1.c: Likewise. * gcc.target/riscv/shorten-memrefs-2.c: Likewise. * gcc.target/riscv/shorten-memrefs-3.c: Likewise. * gcc.target/riscv/shorten-memrefs-4.c: Likewise. * gcc.target/riscv/shorten-memrefs-5.c: Likewise. * gcc.target/riscv/shorten-memrefs-6.c: Likewise. * gcc.target/riscv/shorten-memrefs-7.c: Likewise. * gcc.target/riscv/shorten-memrefs-8.c: Likewise. * gcc.target/riscv/switch-qi.c: Likewise. * gcc.target/riscv/switch-si.c: Likewise. * gcc.target/riscv/weak-1.c: Likewise. * gcc.target/riscv/zba-adduw.c: Likewise. * gcc.target/riscv/zba-shNadd-01.c: Likewise. * gcc.target/riscv/zba-shNadd-02.c: Likewise. * gcc.target/riscv/zba-shNadd-03.c: Likewise. * gcc.target/riscv/zba-slliuw.c: Likewise. * gcc.target/riscv/zba-zextw.c: Likewise. * gcc.target/riscv/zbb-andn-orn-xnor-01.c: Likewise. * gcc.target/riscv/zbb-andn-orn-xnor-02.c: Likewise. * gcc.target/riscv/zbb-li-rotr.c: Likewise. * gcc.target/riscv/zbb-min-max.c: Likewise. * gcc.target/riscv/zbb-rol-ror-01.c: Likewise. * gcc.target/riscv/zbb-rol-ror-02.c: Likewise. * gcc.target/riscv/zbb-rol-ror-03.c: Likewise. * gcc.target/riscv/zbbw.c: Likewise. * gcc.target/riscv/zbs-bclr.c: Likewise. * gcc.target/riscv/zbs-bext.c: Likewise. * gcc.target/riscv/zbs-binv.c: Likewise. * gcc.target/riscv/zbs-bset.c: Likewise. * gcc.target/riscv/zero-extend-1.c: Likewise. * gcc.target/riscv/zero-extend-2.c: Likewise. * gcc.target/riscv/zero-extend-3.c: Likewise. * gcc.target/riscv/zero-extend-4.c: Likewise. * gcc.target/riscv/zero-extend-5.c: Likewise.
author: Maciej W. Rozycki <macro@embecosm.com> 2022-02-08 12:14:59 +0000
committer: Maciej W. Rozycki <macro@embecosm.com> 2022-02-08 12:20:03 +0000
commit: 6de582dd62dfcb18f51e3dd01cf8519a74752530 (patch)
tree: 60b6a31c6d08f3719802556ecf4ab2b43528e2cf
parent: 5e92fddad7719f2f2cdf55f73222c4978af38f35 (diff)
download: gcc-6de582dd62dfcb18f51e3dd01cf8519a74752530.zip
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gcc-6de582dd62dfcb18f51e3dd01cf8519a74752530.tar.bz2
118 files changed, 168 insertions, 117 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/arch-1.c b/gcc/testsuite/gcc.target/riscv/arch-1.c
index 9458977..c271811 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-1.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -march=rv32i -march=rv32I -mabi=ilp32" } */
+/* { dg-options "-march=rv32i -march=rv32I -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/arch-10.c b/gcc/testsuite/gcc.target/riscv/arch-10.c
index 1052f2e..6124055 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-10.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gf2 -mabi=ilp32" } */
+/* { dg-options "-march=rv32gf2 -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/arch-11.c b/gcc/testsuite/gcc.target/riscv/arch-11.c
index 129d8f7..d840a43 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-11.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32g_zicsr2 -mabi=ilp32" } */
+/* { dg-options "-march=rv32g_zicsr2 -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/arch-12.c b/gcc/testsuite/gcc.target/riscv/arch-12.c
index 5ee9a1d..e22df50 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-12.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-12.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64im1p2p3 -mabi=lp64" } */
+/* { dg-options "-march=rv64im1p2p3 -mabi=lp64" } */
 int foo() {}
 /* { dg-error "'-march=rv64im1p2p3': for 'm1p2p\\?', version number with more than 2 level is not supported" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-2.c b/gcc/testsuite/gcc.target/riscv/arch-2.c
index 36b7850..8908b4b 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-2.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -march=rv32ixabc_xfoo -mabi=ilp32" } */
+/* { dg-options "-march=rv32ixabc_xfoo -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/arch-3.c b/gcc/testsuite/gcc.target/riscv/arch-3.c
index 1246994..7aa945e 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-3.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -march=rv32isabc_xbar -mabi=ilp32" } */
+/* { dg-options "-march=rv32isabc_xbar -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/arch-4.c b/gcc/testsuite/gcc.target/riscv/arch-4.c
index 6e55a7e..a125192 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-4.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -march=rv32i2p3_m4p2 -mabi=ilp32" } */
+/* { dg-options "-march=rv32i2p3_m4p2 -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/arch-5.c b/gcc/testsuite/gcc.target/riscv/arch-5.c
index b0a1bd4..2a0f3b7 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-5.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -march=rv32isabc_hghi_zfoo_xbar -mabi=ilp32" } */
+/* { dg-options "-march=rv32isabc_hghi_zfoo_xbar -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/arch-6.c b/gcc/testsuite/gcc.target/riscv/arch-6.c
index b36dccb..606c9df 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-6.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -march=rv32id -mabi=ilp32" } */
+/* { dg-options "-march=rv32id -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/arch-7.c b/gcc/testsuite/gcc.target/riscv/arch-7.c
index 74ab248..f7026f5 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-7.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32i -march=rv32im_s -mabi=ilp32" } */
+/* { dg-options "-march=rv32i -march=rv32im_s -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/arch-8.c b/gcc/testsuite/gcc.target/riscv/arch-8.c
index d7760fc..1b9e51b 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-8.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -march=rv32id_zicsr_zifence -mabi=ilp32" } */
+/* { dg-options "-march=rv32id_zicsr_zifence -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/arch-9.c b/gcc/testsuite/gcc.target/riscv/arch-9.c
index d00e99d..133a42c 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-9.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32g2 -mabi=ilp32" } */
+/* { dg-options "-march=rv32g2 -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-1.c b/gcc/testsuite/gcc.target/riscv/attribute-1.c
index 7150f49..bc919c5 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-1.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute" } */
+/* { dg-options "-mriscv-attribute" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-10.c b/gcc/testsuite/gcc.target/riscv/attribute-10.c
index 26fdd08..1e121a1 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-10.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32i -march=rv32im_sx_unexpectedstring -mabi=ilp32" } */
+/* { dg-options "-march=rv32i -march=rv32im_sx_unexpectedstring -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-11.c b/gcc/testsuite/gcc.target/riscv/attribute-11.c
index 98bd8d4..ad88813 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-11.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -march=rv32id -mabi=ilp32 -misa-spec=2.2" } */
+/* { dg-options "-mriscv-attribute -march=rv32id -mabi=ilp32 -misa-spec=2.2" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-12.c b/gcc/testsuite/gcc.target/riscv/attribute-12.c
index 44fccad..c5e5048 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-12.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -march=rv32ifd -mabi=ilp32 -misa-spec=2.2" } */
+/* { dg-options "-mriscv-attribute -march=rv32ifd -mabi=ilp32 -misa-spec=2.2" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-13.c b/gcc/testsuite/gcc.target/riscv/attribute-13.c
index 1b8f93c..f35b725 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-13.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -march=rv32if3d -mabi=ilp32 -misa-spec=2.2" } */
+/* { dg-options "-mriscv-attribute -march=rv32if3d -mabi=ilp32 -misa-spec=2.2" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-14.c b/gcc/testsuite/gcc.target/riscv/attribute-14.c
index 2591c1f..a5fa089 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-14.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -march=rv32if -mabi=ilp32 -misa-spec=20190608" } */
+/* { dg-options "-mriscv-attribute -march=rv32if -mabi=ilp32 -misa-spec=20190608" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c
index 9cae1a2..59efeb6 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=2.2" } */
+/* { dg-options "-mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=2.2" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c
index f090363..26f961e 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=20190608" } */
+/* { dg-options "-mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=20190608" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c
index 19ef540..0abff37 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-17.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=20191213" } */
+/* { dg-options "-mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=20191213" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-2.c b/gcc/testsuite/gcc.target/riscv/attribute-2.c
index 3636a1a..b8cacae 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-2.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mno-riscv-attribute" } */
+/* { dg-options "-mno-riscv-attribute" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-3.c b/gcc/testsuite/gcc.target/riscv/attribute-3.c
index 735992d..613f3c3 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-3.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -mpreferred-stack-boundary=8" } */
+/* { dg-options "-mriscv-attribute -mpreferred-stack-boundary=8" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-4.c b/gcc/testsuite/gcc.target/riscv/attribute-4.c
index 404faad..7c565c4 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-4.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -mstrict-align" } */
+/* { dg-options "-mriscv-attribute -mstrict-align" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-5.c b/gcc/testsuite/gcc.target/riscv/attribute-5.c
index de89094..ee9cf69 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-5.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -mno-strict-align" } */
+/* { dg-options "-mriscv-attribute -mno-strict-align" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-7.c b/gcc/testsuite/gcc.target/riscv/attribute-7.c
index 3d03393..185730f 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-7.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -march=rv32e1p9 -mabi=ilp32e" } */
+/* { dg-options "-mriscv-attribute -march=rv32e1p9 -mabi=ilp32e" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-8.c b/gcc/testsuite/gcc.target/riscv/attribute-8.c
index 90f5a40..4c91b9e 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-8.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -march=rv32i2p0xabc_xv5 -mabi=ilp32" } */
+/* { dg-options "-mriscv-attribute -march=rv32i2p0xabc_xv5 -mabi=ilp32" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-9.c b/gcc/testsuite/gcc.target/riscv/attribute-9.c
index 4598872..7e3741a 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-9.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -mriscv-attribute -march=rv32i2p0sabc_xbar -mabi=ilp32e" } */
+/* { dg-options "-mriscv-attribute -march=rv32i2p0sabc_xbar -mabi=ilp32e" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-1.c b/gcc/testsuite/gcc.target/riscv/interrupt-1.c
index 666b29a..d85eb98 100644
--- a/gcc/testsuite/gcc.target/riscv/interrupt-1.c
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-1.c
@@ -1,6 +1,6 @@
 /* Verify the return instruction is mret.  */
 /* { dg-do compile } */
-/* { dg-options "-O" } */
+/* { dg-options "" } */
 void __attribute__ ((interrupt))
 foo (void)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-2.c b/gcc/testsuite/gcc.target/riscv/interrupt-2.c
index 82e3fb2..ef50498 100644
--- a/gcc/testsuite/gcc.target/riscv/interrupt-2.c
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-2.c
@@ -1,6 +1,6 @@
 /* Verify that arg regs used as temporaries get saved.  */
 /* { dg-do compile } */
-/* { dg-options "-O" } */
+/* { dg-options "" } */
 void __attribute__ ((interrupt))
 foo2 (void)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-3.c b/gcc/testsuite/gcc.target/riscv/interrupt-3.c
index 3d1d44d..edd2fb6 100644
--- a/gcc/testsuite/gcc.target/riscv/interrupt-3.c
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-3.c
@@ -1,6 +1,7 @@
 /* Verify t0 is saved before use.  */
 /* { dg-do compile } */
-/* { dg-options "-O0 -fomit-frame-pointer" } */
+/* { dg-options "-fomit-frame-pointer" } */
+/* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */
 void __attribute__ ((interrupt))
 foo (void)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-4.c b/gcc/testsuite/gcc.target/riscv/interrupt-4.c
index 658aa17..fc53f08 100644
--- a/gcc/testsuite/gcc.target/riscv/interrupt-4.c
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-4.c
@@ -1,6 +1,7 @@
 /* Verify t0 is saved before use.  */
 /* { dg-do compile } */
-/* { dg-options "-O0 -fomit-frame-pointer" } */
+/* { dg-options "-fomit-frame-pointer" } */
+/* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */
 void __attribute__ ((interrupt))
 foo2 (void)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c b/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c
index e9f1452..81ebf5f 100644
--- a/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c
@@ -1,6 +1,6 @@
 /* Verify proper errors are generated for conflicted interrupt type.  */
 /* { dg-do compile } */
-/* { dg-options "-O" } */
+/* { dg-options "" } */
 void __attribute__ ((interrupt ("user")))
 foo(void);
 
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-debug.c b/gcc/testsuite/gcc.target/riscv/interrupt-debug.c
index a1b6dac..4ad7510 100644
--- a/gcc/testsuite/gcc.target/riscv/interrupt-debug.c
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-debug.c
@@ -1,6 +1,7 @@
 /* Verify that we can compile with debug info.  */
 /* { dg-do compile } */
-/* { dg-options "-Og -g" } */
+/* { dg-options "" } */
+/* { dg-skip-if "" { *-*-* } { "*" } { "-g" } } */
 extern int var1;
 extern int var2;
 extern void sub2 (void);
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c b/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c
index fd7a7a1..50d54a0 100644
--- a/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c
@@ -1,6 +1,6 @@
 /* Verify the return instruction is mret.  */
 /* { dg-do compile } */
-/* { dg-options "-O" } */
+/* { dg-options "" } */
 void __attribute__ ((interrupt ("machine")))
 foo (void)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-smode.c b/gcc/testsuite/gcc.target/riscv/interrupt-smode.c
index 2f696d3..973a9b1 100644
--- a/gcc/testsuite/gcc.target/riscv/interrupt-smode.c
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-smode.c
@@ -1,6 +1,6 @@
 /* Verify the return instruction is mret.  */
 /* { dg-do compile } */
-/* { dg-options "-O" } */
+/* { dg-options "" } */
 void __attribute__ ((interrupt ("supervisor")))
 foo (void)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c b/gcc/testsuite/gcc.target/riscv/interrupt-umode.c
index cd120e4..7fcef755 100644
--- a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-umode.c
@@ -1,6 +1,6 @@
 /* Verify the return instruction is mret.  */
 /* { dg-do compile } */
-/* { dg-options "-O" } */
+/* { dg-options "" } */
 void __attribute__ ((interrupt ("user")))
 foo (void)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/li.c b/gcc/testsuite/gcc.target/riscv/li.c
index fa5c02c..2ade06d 100644
--- a/gcc/testsuite/gcc.target/riscv/li.c
+++ b/gcc/testsuite/gcc.target/riscv/li.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-O1" } */
+/* { dg-options "" } */
 #include <stdlib.h>
 #define LOAD_IMM(var, val) \
         asm ("li %0, %1\n": "=r"(var): "i" (val))
diff --git a/gcc/testsuite/gcc.target/riscv/load-immediate.c b/gcc/testsuite/gcc.target/riscv/load-immediate.c
index f8fe747..6f644d1 100644
--- a/gcc/testsuite/gcc.target/riscv/load-immediate.c
+++ b/gcc/testsuite/gcc.target/riscv/load-immediate.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* Check that we don't have unnecessary load immediate instructions.  */
 void
diff --git a/gcc/testsuite/gcc.target/riscv/losum-overflow.c b/gcc/testsuite/gcc.target/riscv/losum-overflow.c
index 9c01c7f..843abb6 100644
--- a/gcc/testsuite/gcc.target/riscv/losum-overflow.c
+++ b/gcc/testsuite/gcc.target/riscv/losum-overflow.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc -mabi=ilp32 -O2 -fno-section-anchors" } */
+/* { dg-options "-march=rv32gc -mabi=ilp32 -fno-section-anchors" } */
 
 /* Check for %lo overflow.  Adding an offset larger than the alignment can
    overflow if the data is allocated to an address mod 4KB that is between
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-6.c b/gcc/testsuite/gcc.target/riscv/mcpu-6.c
index 57e3345..96faa01 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-6.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-6.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify -mtune has higher priority than -mcpu for pipeline model .  */
-/* { dg-options "-mcpu=sifive-u74 -mtune=rocket -fdump-rtl-sched2-details -O3 -march=rv32i -mabi=ilp32" } */
+/* { dg-options "-mcpu=sifive-u74 -mtune=rocket -fdump-rtl-sched2-details -march=rv32i -mabi=ilp32" } */
 /* { dg-final { scan-rtl-dump "simple_return\[ \]+:alu" "sched2" } } */
 
 int main()
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-7.c b/gcc/testsuite/gcc.target/riscv/mcpu-7.c
index fe3c04b..6832323 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-7.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-7.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify -mtune has higher priority than -mcpu for pipeline model .  */
-/* { dg-options "-mcpu=sifive-s21 -mtune=sifive-u74 -fdump-rtl-sched2-details -O3 -march=rv32i -mabi=ilp32" } */
+/* { dg-options "-mcpu=sifive-s21 -mtune=sifive-u74 -fdump-rtl-sched2-details -march=rv32i -mabi=ilp32" } */
 /* { dg-final { scan-rtl-dump "simple_return\[ \]+:sifive_7_B" "sched2" } } */
 
 int main()
diff --git a/gcc/testsuite/gcc.target/riscv/pr102957.c b/gcc/testsuite/gcc.target/riscv/pr102957.c
index 8a7e541..9747dde 100644
--- a/gcc/testsuite/gcc.target/riscv/pr102957.c
+++ b/gcc/testsuite/gcc.target/riscv/pr102957.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -march=rv64gzb -mabi=lp64" } */
+/* { dg-options "-march=rv64gzb -mabi=lp64" } */
 int foo()
 {
 }
diff --git a/gcc/testsuite/gcc.target/riscv/pr103302.c b/gcc/testsuite/gcc.target/riscv/pr103302.c
index cfaa222..87ee630 100644
--- a/gcc/testsuite/gcc.target/riscv/pr103302.c
+++ b/gcc/testsuite/gcc.target/riscv/pr103302.c
@@ -1,5 +1,6 @@
 /* { dg-do run { target int128 } } */
-/* { dg-options "-Og -fharden-compares -fno-tree-dce -fno-tree-fre " } */
+/* { dg-options "-fharden-compares -fno-tree-dce -fno-tree-fre" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 typedef unsigned char u8;
 typedef unsigned char __attribute__((__vector_size__ (32))) v256u8;
diff --git a/gcc/testsuite/gcc.target/riscv/pr104140.c b/gcc/testsuite/gcc.target/riscv/pr104140.c
index 648e131..61705f4 100644
--- a/gcc/testsuite/gcc.target/riscv/pr104140.c
+++ b/gcc/testsuite/gcc.target/riscv/pr104140.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32im -mabi=ilp32" } */
+/* { dg-options "-march=rv32im -mabi=ilp32" } */
 int x;
 unsigned u, v;
 void f (void)
diff --git a/gcc/testsuite/gcc.target/riscv/pr84660.c b/gcc/testsuite/gcc.target/riscv/pr84660.c
index a87fa0a..b6d19f3 100644
--- a/gcc/testsuite/gcc.target/riscv/pr84660.c
+++ b/gcc/testsuite/gcc.target/riscv/pr84660.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-O2" } */
+/* { dg-options "" } */
 
 extern void abort (void);
 extern void exit (int);
diff --git a/gcc/testsuite/gcc.target/riscv/pr93202.c b/gcc/testsuite/gcc.target/riscv/pr93202.c
index d8091b9..5501191 100644
--- a/gcc/testsuite/gcc.target/riscv/pr93202.c
+++ b/gcc/testsuite/gcc.target/riscv/pr93202.c
@@ -1,6 +1,7 @@
 /* PR inline-asm/93202 */
 /* { dg-do compile { target fpic } } */
 /* { dg-options "-fpic" } */
+/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
 
 void
 foo (void)
diff --git a/gcc/testsuite/gcc.target/riscv/pr93304.c b/gcc/testsuite/gcc.target/riscv/pr93304.c
index 248f205..ce2dc4d 100644
--- a/gcc/testsuite/gcc.target/riscv/pr93304.c
+++ b/gcc/testsuite/gcc.target/riscv/pr93304.c
@@ -1,7 +1,8 @@
 /* Verify the regrename won't rename registers to register which never used
    before.  */
 /* { dg-do compile } */
-/* { dg-options "-O -frename-registers" } */
+/* { dg-options "-frename-registers" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 static unsigned _t = 0;
 
diff --git a/gcc/testsuite/gcc.target/riscv/pr95252.c b/gcc/testsuite/gcc.target/riscv/pr95252.c
index 0366c08..92fef59 100644
--- a/gcc/testsuite/gcc.target/riscv/pr95252.c
+++ b/gcc/testsuite/gcc.target/riscv/pr95252.c
@@ -1,6 +1,7 @@
 /* PR target/95252 */
-/* { dg-options "-O3 -funroll-loops -msave-restore" } */
+/* { dg-options "-funroll-loops -msave-restore" } */
 /* { dg-do run } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 int a[6], b = 1, d, e;
 long long c;
diff --git a/gcc/testsuite/gcc.target/riscv/pr95683.c b/gcc/testsuite/gcc.target/riscv/pr95683.c
index 00cfbdc..5049c04 100644
--- a/gcc/testsuite/gcc.target/riscv/pr95683.c
+++ b/gcc/testsuite/gcc.target/riscv/pr95683.c
@@ -1,5 +1,5 @@
 /* PR target/95683 */
-/* { dg-options "-Os" } */
+/* { dg-options "" } */
 /* { dg-do compile } */
 void a() {
   asm(""
diff --git a/gcc/testsuite/gcc.target/riscv/pr98777.c b/gcc/testsuite/gcc.target/riscv/pr98777.c
index ea2c2f9..0be734b 100644
--- a/gcc/testsuite/gcc.target/riscv/pr98777.c
+++ b/gcc/testsuite/gcc.target/riscv/pr98777.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-fstrict-aliasing -O" } */
+/* { dg-options "-fstrict-aliasing" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 typedef struct {
   _Complex e;
diff --git a/gcc/testsuite/gcc.target/riscv/pr99702.c b/gcc/testsuite/gcc.target/riscv/pr99702.c
index a28724c..b7db184 100644
--- a/gcc/testsuite/gcc.target/riscv/pr99702.c
+++ b/gcc/testsuite/gcc.target/riscv/pr99702.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O" } */
+/* { dg-options "" } */
 char n;
 void *i, *j;
 void foo(void) {
diff --git a/gcc/testsuite/gcc.target/riscv/predef-1.c b/gcc/testsuite/gcc.target/riscv/predef-1.c
index 70f121f..2e57ce6 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-1.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32i -mabi=ilp32 -mcmodel=medlow" } */
+/* { dg-options "-march=rv32i -mabi=ilp32 -mcmodel=medlow" } */
 
 int main () {
 #if !defined(__riscv)
diff --git a/gcc/testsuite/gcc.target/riscv/predef-10.c b/gcc/testsuite/gcc.target/riscv/predef-10.c
index 7c447bf..c1a39b6 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-10.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32i2p0 -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
+/* { dg-options "-march=rv32i2p0 -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
 
 int main () {
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-11.c b/gcc/testsuite/gcc.target/riscv/predef-11.c
index 80f4811..ef6beca 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-11.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
 
 int main () {
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-12.c b/gcc/testsuite/gcc.target/riscv/predef-12.c
index dd35dbd..eed5fc8 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-12.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc -mabi=lp64 -mcmodel=medlow -misa-spec=20191213" } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=medlow -misa-spec=20191213" } */
 
 int main () {
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-13.c b/gcc/testsuite/gcc.target/riscv/predef-13.c
index 95cf001..3836255 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-13.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32e -mabi=ilp32e -mcmodel=medlow -misa-spec=2.2" } */
+/* { dg-options "-march=rv32e -mabi=ilp32e -mcmodel=medlow -misa-spec=2.2" } */
 
 int main () {
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-14.c b/gcc/testsuite/gcc.target/riscv/predef-14.c
index 108fc0c..4815150 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-14.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32iv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
+/* { dg-options "-march=rv32iv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
 
 int main () {
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-15.c b/gcc/testsuite/gcc.target/riscv/predef-15.c
index a37c457..dad1495 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-15.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64iv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
+/* { dg-options "-march=rv64iv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
 
 int main () {
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-16.c b/gcc/testsuite/gcc.target/riscv/predef-16.c
index 6c5c874..faebc1ab4 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-16.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64i_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
+/* { dg-options "-march=rv64i_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
 
 int main () {
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-2.c b/gcc/testsuite/gcc.target/riscv/predef-2.c
index 6f3c8c38..c85b3c9 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-2.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32imaf -mabi=ilp32f -mcmodel=medany" } */
+/* { dg-options "-march=rv32imaf -mabi=ilp32f -mcmodel=medany" } */
 
 int main () {
 #if !defined(__riscv)
diff --git a/gcc/testsuite/gcc.target/riscv/predef-3.c b/gcc/testsuite/gcc.target/riscv/predef-3.c
index d7c9793..82a89d4 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-3.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32imafdc -mabi=ilp32d -fpic" } */
+/* { dg-options "-march=rv32imafdc -mabi=ilp32d -fpic" } */
 
 int main () {
 #if !defined(__riscv)
diff --git a/gcc/testsuite/gcc.target/riscv/predef-4.c b/gcc/testsuite/gcc.target/riscv/predef-4.c
index 822f617..5868d39 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-4.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64ia -mabi=lp64 -mcmodel=medlow" } */
+/* { dg-options "-march=rv64ia -mabi=lp64 -mcmodel=medlow" } */
 
 int main () {
 #if !defined(__riscv)
diff --git a/gcc/testsuite/gcc.target/riscv/predef-5.c b/gcc/testsuite/gcc.target/riscv/predef-5.c
index 6649049..4b2bd38 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-5.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64imf -mabi=lp64f -mcmodel=medany" } */
+/* { dg-options "-march=rv64imf -mabi=lp64f -mcmodel=medany" } */
 
 int main () {
 #if !defined(__riscv)
diff --git a/gcc/testsuite/gcc.target/riscv/predef-6.c b/gcc/testsuite/gcc.target/riscv/predef-6.c
index 7530f95..8e5ea36 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-6.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -fpic" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fpic" } */
 
 int main () {
 #if !defined(__riscv)
diff --git a/gcc/testsuite/gcc.target/riscv/predef-7.c b/gcc/testsuite/gcc.target/riscv/predef-7.c
index 0358f32..0bde299 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-7.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow" } */
+/* { dg-options "-march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow" } */
 
 int main () {
 #if !defined(__riscv)
diff --git a/gcc/testsuite/gcc.target/riscv/predef-8.c b/gcc/testsuite/gcc.target/riscv/predef-8.c
index 41cd9fe..18aa591 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-8.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32if -mabi=ilp32f -mno-fdiv -mcmodel=medany" } */
+/* { dg-options "-march=rv32if -mabi=ilp32f -mno-fdiv -mcmodel=medany" } */
 
 int main () {
 #if !defined(__riscv)
diff --git a/gcc/testsuite/gcc.target/riscv/promote-type-for-libcall.c b/gcc/testsuite/gcc.target/riscv/promote-type-for-libcall.c
index bdbcbc0..cd313ea 100644
--- a/gcc/testsuite/gcc.target/riscv/promote-type-for-libcall.c
+++ b/gcc/testsuite/gcc.target/riscv/promote-type-for-libcall.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
-/* { dg-options "-O1 -ftree-slp-vectorize -funroll-loops" } */
+/* { dg-options "-ftree-slp-vectorize -funroll-loops" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 #include <stdio.h>
 #include <stdlib.h>
diff --git a/gcc/testsuite/gcc.target/riscv/riscv.exp b/gcc/testsuite/gcc.target/riscv/riscv.exp
index c0b97ed..9b7ec56 100644
--- a/gcc/testsuite/gcc.target/riscv/riscv.exp
+++ b/gcc/testsuite/gcc.target/riscv/riscv.exp
@@ -21,6 +21,8 @@ if ![istarget riscv*-*-*] then {
   return
 }
 
+lappend ADDITIONAL_TORTURE_OPTIONS {-Og -g} {-Oz}
+
 # Load support procs.
 load_lib gcc-dg.exp
 
@@ -34,7 +36,7 @@ if ![info exists DEFAULT_CFLAGS] then {
 dg-init
 
 # Main loop.
-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
 	"" $DEFAULT_CFLAGS
 
 # All done.
diff --git a/gcc/testsuite/gcc.target/riscv/save-restore-1.c b/gcc/testsuite/gcc.target/riscv/save-restore-1.c
index 35b08b9..7e3737d 100644
--- a/gcc/testsuite/gcc.target/riscv/save-restore-1.c
+++ b/gcc/testsuite/gcc.target/riscv/save-restore-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-O2 -msave-restore -fomit-frame-pointer" } */
+/* { dg-options "-msave-restore -fomit-frame-pointer" } */
 
 #include <stdlib.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/save-restore-2.c b/gcc/testsuite/gcc.target/riscv/save-restore-2.c
index 204bf67..eef8964 100644
--- a/gcc/testsuite/gcc.target/riscv/save-restore-2.c
+++ b/gcc/testsuite/gcc.target/riscv/save-restore-2.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -msave-restore" } */
+/* { dg-options "-msave-restore" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* With -msave-restore in use it should not be possible to remove the calls
    to the save and restore stubs in this case (in current GCC).  */
diff --git a/gcc/testsuite/gcc.target/riscv/save-restore-3.c b/gcc/testsuite/gcc.target/riscv/save-restore-3.c
index 6bf9fb0..d5304b6 100644
--- a/gcc/testsuite/gcc.target/riscv/save-restore-3.c
+++ b/gcc/testsuite/gcc.target/riscv/save-restore-3.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -msave-restore" } */
+/* { dg-options "-msave-restore" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
 
 /* With -msave-restore in use GCC should be able to remove the calls to the
    save and restore stubs in this case, replacing them with a tail call to
diff --git a/gcc/testsuite/gcc.target/riscv/save-restore-4.c b/gcc/testsuite/gcc.target/riscv/save-restore-4.c
index 9a0313f..eefce60 100644
--- a/gcc/testsuite/gcc.target/riscv/save-restore-4.c
+++ b/gcc/testsuite/gcc.target/riscv/save-restore-4.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -msave-restore" } */
+/* { dg-options "-msave-restore" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
 
 /* This test covers a case where we can't (currently) remove the calls to
    the save/restore stubs.  The cast of the return value from BAR requires
diff --git a/gcc/testsuite/gcc.target/riscv/save-restore-6.c b/gcc/testsuite/gcc.target/riscv/save-restore-6.c
index 5308654..31c6774 100644
--- a/gcc/testsuite/gcc.target/riscv/save-restore-6.c
+++ b/gcc/testsuite/gcc.target/riscv/save-restore-6.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -msave-restore" } */
+/* { dg-options "-msave-restore" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* With -msave-restore in use GCC should be able to remove the calls to the
    save and restore stubs in this case, replacing them with a tail call to
diff --git a/gcc/testsuite/gcc.target/riscv/save-restore-7.c b/gcc/testsuite/gcc.target/riscv/save-restore-7.c
index 06719c4..8ef38b0 100644
--- a/gcc/testsuite/gcc.target/riscv/save-restore-7.c
+++ b/gcc/testsuite/gcc.target/riscv/save-restore-7.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -msave-restore" } */
+/* { dg-options "-msave-restore" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
 
 /* With -msave-restore in use it should not be possible to remove the calls
    to the save and restore stubs in this case (in current GCC).  */
diff --git a/gcc/testsuite/gcc.target/riscv/save-restore-8.c b/gcc/testsuite/gcc.target/riscv/save-restore-8.c
index 8880cd2..3794173 100644
--- a/gcc/testsuite/gcc.target/riscv/save-restore-8.c
+++ b/gcc/testsuite/gcc.target/riscv/save-restore-8.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -msave-restore" } */
+/* { dg-options "-msave-restore" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* As a leaf function this should never have the calls to the save and
    restore stubs added, but lets check anyway.  */
diff --git a/gcc/testsuite/gcc.target/riscv/save-restore-9.c b/gcc/testsuite/gcc.target/riscv/save-restore-9.c
index 2567dae..dc90137 100644
--- a/gcc/testsuite/gcc.target/riscv/save-restore-9.c
+++ b/gcc/testsuite/gcc.target/riscv/save-restore-9.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
-/* { dg-options "-O2 -msave-restore" } */
+/* { dg-options "-msave-restore" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 int
 __attribute__((noinline,noclone))
diff --git a/gcc/testsuite/gcc.target/riscv/shift-and-1.c b/gcc/testsuite/gcc.target/riscv/shift-and-1.c
index d1f3a05..429ab84f 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-and-1.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-and-1.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc -mabi=ilp32 -O" } */
+/* { dg-options "-march=rv32gc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* Test for <optab>si3_mask.  */
 int
diff --git a/gcc/testsuite/gcc.target/riscv/shift-and-2.c b/gcc/testsuite/gcc.target/riscv/shift-and-2.c
index 2c98e50..360d841 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-and-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-and-2.c
@@ -1,5 +1,6 @@
 /* { dg-do compile { target { riscv64*-*-* } } } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* Test for <optab>si3_mask_1.  */
 extern int k;
diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-1.c b/gcc/testsuite/gcc.target/riscv/shift-shift-1.c
index a5343a3..462e532 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-1.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc -mabi=ilp32 -O" } */
+/* { dg-options "-march=rv32gc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
 
 /* Test for lshrsi3_zero_extend_3+1 pattern that uses p2m1_shift_operand.  */
 unsigned int
diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
index 10a5bb7..5f93be1 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
 
 /* Test for lshrsi3_zero_extend_3+1 pattern that uses p2m1_shift_operand.  */
 unsigned int
diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-3.c b/gcc/testsuite/gcc.target/riscv/shift-shift-3.c
index c974e75..16999b0 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-3.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
 
 /* Test for lshrsi3_zero_extend_3+2 pattern that uses
    high_mask_shift_operand.  */
diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-4.c b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c
index 72a45ee..bc7bca1 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-shift-4.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32i -mabi=ilp32 -O2" } */
+/* { dg-options "-march=rv32i -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
 
 /* One zero-extend shift can be eliminated by modifying the constant in the
    greater than test.  Started working after modifying the splitter
diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
index 0ecab97..ed8e7b3 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
 
 /* Fails if lshrsi3_zero_extend_3+1 uses a temp reg which has no REG_DEST
    note.  */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
index 958942a..f0222f4 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
 
 /* These stores cannot be compressed because x0 is not a compressed reg.
    Therefore the shorten_memrefs pass should not attempt to rewrite them into a
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
index 2c2f415..ec39104 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
 
 /* shorten_memrefs should rewrite these load/stores into a compressible
    format.  */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
index 2001fe8..5031628 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
 
 /* These loads cannot be compressed because only one compressed reg is
    available (since args are passed in a0-a4, that leaves a5-a7 available, of
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
index cd47849..d985512 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -march=rv64imc -mabi=lp64" } */
+/* { dg-options "-march=rv64imc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
 
 /* These stores cannot be compressed because x0 is not a compressed reg.
    Therefore the shorten_memrefs pass should not attempt to rewrite them into a
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
index 80b3897..9217922 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -march=rv64imc -mabi=lp64" } */
+/* { dg-options "-march=rv64imc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
 
 /* shorten_memrefs should rewrite these load/stores into a compressible
    format.  */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c
index 3403c70..c36af6d 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -march=rv64imc -mabi=lp64" } */
+/* { dg-options "-march=rv64imc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
 
 /* These loads cannot be compressed because only one compressed reg is
    available (since args are passed in a0-a4, that leaves a5-a7 available, of
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c
index a5833fd..476d079 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -march=rv32imc -mabi=ilp32 -mno-shorten-memrefs" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32 -mno-shorten-memrefs" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* Check that these load/stores do not get rewritten into a compressible format
    when shorten_memrefs is disabled.  */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
index a9128ca..6dfc015 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
@@ -1,4 +1,5 @@
-/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
 
 /* shorten_memrefs should use a correct base address*/
 
diff --git a/gcc/testsuite/gcc.target/riscv/switch-qi.c b/gcc/testsuite/gcc.target/riscv/switch-qi.c
index 973d09a..e39219b 100644
--- a/gcc/testsuite/gcc.target/riscv/switch-qi.c
+++ b/gcc/testsuite/gcc.target/riscv/switch-qi.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { riscv64*-*-* } } } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
 
 /* Test for riscv_extend_comparands patch.  */
 extern void asdf(int);
diff --git a/gcc/testsuite/gcc.target/riscv/switch-si.c b/gcc/testsuite/gcc.target/riscv/switch-si.c
index de4d68f..c68f98d 100644
--- a/gcc/testsuite/gcc.target/riscv/switch-si.c
+++ b/gcc/testsuite/gcc.target/riscv/switch-si.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "" } */
 
 /* Test for do_tablejump patch.  */
 extern void asdf(int);
diff --git a/gcc/testsuite/gcc.target/riscv/weak-1.c b/gcc/testsuite/gcc.target/riscv/weak-1.c
index 0f20501..cc89fa2 100644
--- a/gcc/testsuite/gcc.target/riscv/weak-1.c
+++ b/gcc/testsuite/gcc.target/riscv/weak-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mcmodel=medany -mexplicit-relocs -O" } */
+/* { dg-options "-mcmodel=medany -mexplicit-relocs" } */
 
 /* Verify that the branch doesn't get optimized away.  */
 extern int weak_func(void) __attribute__ ((weak));
diff --git a/gcc/testsuite/gcc.target/riscv/zba-adduw.c b/gcc/testsuite/gcc.target/riscv/zba-adduw.c
index cac1e84..2ae03ae 100644
--- a/gcc/testsuite/gcc.target/riscv/zba-adduw.c
+++ b/gcc/testsuite/gcc.target/riscv/zba-adduw.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 int foo(int n, unsigned char *arr, unsigned y){
   int s = 0;
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
index aaabaf5..bc97bc7 100644
--- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 long test_1(long a, long b)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
index 8dfea4a..5f4b65f 100644
--- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zba -mabi=ilp32 -O2" } */
+/* { dg-options "-march=rv32gc_zba -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 long test_1(long a, long b)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
index b2ea231..8352274 100644
--- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* RV64 only.  */
 int foos(short *x, int n){
diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
index a7a3dc7..cd3cf0e 100644
--- a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
+++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" } } */
 
 long
 foo (long i)
diff --git a/gcc/testsuite/gcc.target/riscv/zba-zextw.c b/gcc/testsuite/gcc.target/riscv/zba-zextw.c
index 26fd64d..271c186 100644
--- a/gcc/testsuite/gcc.target/riscv/zba-zextw.c
+++ b/gcc/testsuite/gcc.target/riscv/zba-zextw.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 long
 foo (long i)
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
index 0037dea..89a3043 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
 
 unsigned long long foo1(unsigned long long rs1, unsigned long long rs2)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
index b0c1e40..ef0dade 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
 
 unsigned int foo1(unsigned int rs1, unsigned int rs2)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c b/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
index 03254ed..500264a 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
 
 long
 li_rori (void)
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
index f44c398..ce054dd 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
 
 long
 foo1 (long i, long j)
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
index 9589662..20c1b28 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
 
 unsigned long foo1(unsigned long rs1, unsigned long rs2)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
index 24b482f..14196c1 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
 
 unsigned int foo1(unsigned int rs1, unsigned int rs2)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
index ffde7c9..ed4685d 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* RV64 only*/
 unsigned int rol(unsigned int rs1, unsigned int rs2)
diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c
index 236ddf7..709743c 100644
--- a/gcc/testsuite/gcc.target/riscv/zbbw.c
+++ b/gcc/testsuite/gcc.target/riscv/zbbw.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
 
 int
 clz (int i)
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bclr.c b/gcc/testsuite/gcc.target/riscv/zbs-bclr.c
index 4a3c2f1..5d7daa3 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bclr.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bclr.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
 
 /* bclr */
 long
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
index a093cdc..4798239 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* bext */
 long
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-binv.c b/gcc/testsuite/gcc.target/riscv/zbs-binv.c
index e4e48b9..d8d6e47 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-binv.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-binv.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* binv */
 long
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bset.c b/gcc/testsuite/gcc.target/riscv/zbs-bset.c
index 733d427..cea2b64 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bset.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bset.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 /* bset */
 long
diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-1.c b/gcc/testsuite/gcc.target/riscv/zero-extend-1.c
index 8a7d84d..b61ea8e 100644
--- a/gcc/testsuite/gcc.target/riscv/zero-extend-1.c
+++ b/gcc/testsuite/gcc.target/riscv/zero-extend-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { riscv64*-*-* } } } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
 unsigned long
 sub1 (unsigned int i)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-2.c b/gcc/testsuite/gcc.target/riscv/zero-extend-2.c
index 9d30ae2..c3d6eeb 100644
--- a/gcc/testsuite/gcc.target/riscv/zero-extend-2.c
+++ b/gcc/testsuite/gcc.target/riscv/zero-extend-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { riscv64*-*-* } } } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
 void
 sub (unsigned int wc, unsigned long step, unsigned char *start)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-3.c b/gcc/testsuite/gcc.target/riscv/zero-extend-3.c
index eb3b8d4..6485ebd 100644
--- a/gcc/testsuite/gcc.target/riscv/zero-extend-3.c
+++ b/gcc/testsuite/gcc.target/riscv/zero-extend-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { riscv64*-*-* } } } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
 extern int e (void);
 enum { a, b }
 c (void)
diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-4.c b/gcc/testsuite/gcc.target/riscv/zero-extend-4.c
index d7703a6..e1a8922 100644
--- a/gcc/testsuite/gcc.target/riscv/zero-extend-4.c
+++ b/gcc/testsuite/gcc.target/riscv/zero-extend-4.c
@@ -1,5 +1,6 @@
 /* { dg-do compile { target { riscv64*-*-* } } } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 int a, b, e;
 struct c *d;
 struct c
diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-5.c b/gcc/testsuite/gcc.target/riscv/zero-extend-5.c
index 1a135b8..4e58a15 100644
--- a/gcc/testsuite/gcc.target/riscv/zero-extend-5.c
+++ b/gcc/testsuite/gcc.target/riscv/zero-extend-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { riscv64*-*-* } } } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
 int
 sub (unsigned int i, unsigned int j, unsigned int k, int *array)
 {
author	Maciej W. Rozycki <macro@embecosm.com>	2022-02-08 12:14:59 +0000
committer	Maciej W. Rozycki <macro@embecosm.com>	2022-02-08 12:20:03 +0000
commit	6de582dd62dfcb18f51e3dd01cf8519a74752530 (patch)
tree	60b6a31c6d08f3719802556ecf4ab2b43528e2cf
parent	5e92fddad7719f2f2cdf55f73222c4978af38f35 (diff)
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