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authorRichard Earnshaw <rearnsha@arm.com>2009-07-23 15:02:20 +0000
committerRichard Earnshaw <rearnsha@gcc.gnu.org>2009-07-23 15:02:20 +0000
commit6d53a79fde65d6d9bcfd445a250e9c3d2c92c703 (patch)
tree1e36eb3a589301af7a0943d6ffdcd759889ae313
parentfa89660f9ac3de88b0dbd12403b720d8179eeca1 (diff)
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(split for ior/xor with shift and zero-extend): Cast op3 to
unsigned HWI. From-SVN: r150013
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/arm/arm.md2
2 files changed, 6 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 746938a..9c56aae 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2009-07-23 Richard Earnshaw <rearnsha@arm.com>
+
+ (split for ior/xor with shift and zero-extend): Cast op3 to
+ unsigned HWI.
+
2009-07-23 Uros Bizjak <ubizjak@gmail.com>
PR target/40832
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 7aaa4c6..863a670 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4219,7 +4219,7 @@
(match_operator 5 "subreg_lowpart_operator"
[(match_operand:SI 4 "s_register_operand" "")]))))]
"TARGET_32BIT
- && (INTVAL (operands[3])
+ && ((unsigned HOST_WIDE_INT) INTVAL (operands[3])
== (GET_MODE_MASK (GET_MODE (operands[5]))
& (GET_MODE_MASK (GET_MODE (operands[5]))
<< (INTVAL (operands[2])))))"