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| author | Patrick O'Neill <patrick@rivosinc.com> | 2023-10-30 09:30:01 -0700 |
|---|---|---|
| committer | Patrick O'Neill <patrick@rivosinc.com> | 2023-10-30 09:58:54 -0700 |
| commit | 68880e40533c41c89eb72247c3080703ad09270c (patch) | |
| tree | a7ff9e21fe7033c2a456a96d1681d38ca67fb8c2 | |
| parent | a3da9adeb457d4f01c4e695a9621f90c2e2a5e68 (diff) | |
| download | gcc-68880e40533c41c89eb72247c3080703ad09270c.zip gcc-68880e40533c41c89eb72247c3080703ad09270c.tar.gz gcc-68880e40533c41c89eb72247c3080703ad09270c.tar.bz2 | |
RISC-V: Make rv32i_zcmp testcase more robust
GCC recently changed its register allocator which causes this
testcase to fail.
This patch updates the regex to be more robust to change by accepting
any s register in the range of 1-9 for cm.push and cm.popret insns.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rv32i_zcmp.c: Accept any register in the
range of 1-9 for cm.push and cm.popret insns.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c index ea562b7..1e1a8be 100644 --- a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c @@ -26,9 +26,9 @@ f2 (void); /* **test1: ** ... -** cm.push {ra, s0-s4}, -80 +** cm.push {ra, s0-s[1-9]}, -80 ** ... -** cm.popret {ra, s0-s4}, 80 +** cm.popret {ra, s0-s[1-9]}, 80 ** ... */ int @@ -50,9 +50,9 @@ test1 () /* **test2_step1_0_size: ** ... -** cm.push {ra, s0-s1}, -64 +** cm.push {ra, s0-s[1-9]}, -64 ** ... -** cm.popret {ra, s0-s1}, 64 +** cm.popret {ra, s0-s[1-9]}, 64 ** ... */ int @@ -70,9 +70,9 @@ test2_step1_0_size () /* **test3: ** ... -** cm.push {ra, s0-s4}, -80 +** cm.push {ra, s0-s[1-9]}, -80 ** ... -** cm.popret {ra, s0-s4}, 80 +** cm.popret {ra, s0-s[1-9]}, 80 ** ... */ float |