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| author | Jeff Law <jlaw@ventanamicro.com> | 2023-08-27 12:52:38 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-08-27 12:52:38 -0600 |
| commit | 6567837fd823a93f7f7948a73ff9dc1153592e8c (patch) | |
| tree | dce1b975149173c243374a125b06dd82c6fd5b23 | |
| parent | b3b13fb1cbad6e5836dee947e85d2954bcacabed (diff) | |
| download | gcc-6567837fd823a93f7f7948a73ff9dc1153592e8c.zip gcc-6567837fd823a93f7f7948a73ff9dc1153592e8c.tar.gz gcc-6567837fd823a93f7f7948a73ff9dc1153592e8c.tar.bz2 | |
RISC-V: Fix spill-12 test
Jivan's recent work on IRA results in more efficient code for this test. This
adjusts the expected output for the removal of 5 instructions and conversion of
an addi into a simple mv.
gcc/testsuite
* gcc.target/riscv/rvv/base/spill-12.c: Update expected output.
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c index de6e060..7e83cb7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c @@ -15,12 +15,7 @@ void fn3 (char*); ** addi\tt0,t0,192 ** add\tsp,sp,t0 ** ... -** li\ta0,-8192 -** addi\ta0,a0,192 -** li\ta5,8192 -** addi\ta5,a5,-192 -** add\ta5,a5,a0 -** add\ta0,a5,sp +** mv\ta0,sp ** ... ** tail\t__riscv_restore_0 */ |