diff options
| author | Uros Bizjak <ubizjak@gmail.com> | 2016-06-26 22:56:34 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2016-06-26 22:56:34 +0200 |
| commit | 6423315e77dafcaec5e6f85b6451fa9bd9562e2d (patch) | |
| tree | bc81aa819f6b38fcbad551dd21c7d37ff6e3336d | |
| parent | 9bb86f403f3085d0d9b344127f7603d4559370a5 (diff) | |
| download | gcc-6423315e77dafcaec5e6f85b6451fa9bd9562e2d.zip gcc-6423315e77dafcaec5e6f85b6451fa9bd9562e2d.tar.gz gcc-6423315e77dafcaec5e6f85b6451fa9bd9562e2d.tar.bz2 | |
re PR rtl-optimization/70902 (GCC freezes while compiling for 'skylake-avx512' target)
PR target/70902
PR target/71453
PR target/71555
PR target/71596
PR target/71657
* config/i386/i386.c (TARGET_SPILL_CLASS): #if 0 out the definition.
(ix86_spill_class): Disable to always return NO_REGS.
From-SVN: r237792
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 8 |
2 files changed, 17 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e153a89..70b7719 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2016-06-26 Uros Bizjak <ubizjak@gmail.com> + + PR target/70902 + PR target/71453 + PR target/71555 + PR target/71596 + PR target/71657 + * config/i386/i386.c (TARGET_SPILL_CLASS): #if 0 out the definition. + (ix86_spill_class): Disable to always return NO_REGS. + 2016-06-26 Jan Hubicka <hubicka@ucw.cz> * predict.c: Include gimple-pretty-print.h diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index f7944f9..c9595fa 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -54583,10 +54583,13 @@ ix86_get_mask_mode (unsigned nunits, unsigned vector_size) /* Return class of registers which could be used for pseudo of MODE and of class RCLASS for spilling instead of memory. Return NO_REGS if it is not possible or non-profitable. */ + +/* Disabled due to PRs 70902, 71453, 71555, 71596 and 71657. */ + static reg_class_t ix86_spill_class (reg_class_t rclass, machine_mode mode) { - if (TARGET_GENERAL_REGS_SSE_SPILL + if (0 && TARGET_GENERAL_REGS_SSE_SPILL && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC && TARGET_INTER_UNIT_MOVES_FROM_VEC @@ -55700,8 +55703,11 @@ ix86_addr_space_zero_address_valid (addr_space_t as) #undef TARGET_LOOP_UNROLL_ADJUST #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust +#if 0 +/* Disabled due to PRs 70902, 71453, 71555, 71596 and 71657. */ #undef TARGET_SPILL_CLASS #define TARGET_SPILL_CLASS ix86_spill_class +#endif #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \ |