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| author | Li Xu <xuli1@eswincomputing.com> | 2023-04-02 21:58:52 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-04-02 21:59:33 -0600 |
| commit | 63e95a83cedd95e4b054dbd602082b0622e55a33 (patch) | |
| tree | b41ac7cbbb816f7ac227f2c01a3662089a73240d | |
| parent | 0580ea4b7a6dc8ee981b08f936b3ce62c6dfe200 (diff) | |
| download | gcc-63e95a83cedd95e4b054dbd602082b0622e55a33.zip gcc-63e95a83cedd95e4b054dbd602082b0622e55a33.tar.gz gcc-63e95a83cedd95e4b054dbd602082b0622e55a33.tar.bz2 | |
RISC-V: Fix typo
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo.
(vfloat32m8_t): Likewise
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins.def | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index d4a74be..2d527f7 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -234,7 +234,7 @@ DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, uint32, VNx16SI, VNx8SI, _u32m8, _u32, _e32m8) /* SEW = 64: - Disable when TARGET_MIN_VLEN > 32. */ + Enable when TARGET_MIN_VLEN > 32. */ DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, int64, VNx1DI, VOID, _i64m1, _i64, _e64m1) DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, uint64, VNx1DI, VOID, _u64m1, @@ -278,7 +278,7 @@ DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8SF, _f32m8, _f32, _e32m8) /* SEW = 64: - Disable when TARGET_VECTOR_FP64. */ + Enable when TARGET_VECTOR_FP64. */ DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID, _f64m1, _f64, _e64m1) DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID, _f64m2, |