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| author | Alexander Nesterovskiy <alexander.nesterovskiy@intel.com> | 2018-05-21 11:14:14 +0000 |
|---|---|---|
| committer | Sebastian Peryt <speryt@gcc.gnu.org> | 2018-05-21 13:14:14 +0200 |
| commit | 60801ebc33261a28cc9225e12b8a425d64a7e314 (patch) | |
| tree | 6c7a4cf8bfbbaa18e2a62d504d27c07f2e75bc96 | |
| parent | d21052ebd7ac9d545a26dde3229c57f872c1d5f3 (diff) | |
| download | gcc-60801ebc33261a28cc9225e12b8a425d64a7e314.zip gcc-60801ebc33261a28cc9225e12b8a425d64a7e314.tar.gz gcc-60801ebc33261a28cc9225e12b8a425d64a7e314.tar.bz2 | |
i386.md (*movsf_internal): AVX falsedep fix.
2018-05-21 Alexander Nesterovskiy <alexander.nesterovskiy@intel.com>
gcc/
* config/i386/i386.md (*movsf_internal): AVX falsedep fix.
(*movdf_internal): Ditto.
(*rcpsf2_sse): Ditto.
(*rsqrtsf2_sse): Ditto.
(*sqrt<mode>2_sse): Ditto.
From-SVN: r260436
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 28 |
2 files changed, 25 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 27b5c60..b1a9017 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2018-05-21 Alexander Nesterovskiy <alexander.nesterovskiy@intel.com> + + * config/i386/i386.md (*movsf_internal): AVX falsedep fix. + (*movdf_internal): Ditto. + (*rcpsf2_sse): Ditto. + (*rsqrtsf2_sse): Ditto. + (*sqrt<mode>2_sse): Ditto. + 2018-05-21 Tamar Christina <tamar.christina@arm.com> * config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 706b7f5..cc993b3 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3559,7 +3559,7 @@ { case MODE_DF: if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1])) - return "vmovsd\t{%1, %0, %0|%0, %0, %1}"; + return "vmovsd\t{%d1, %0|%0, %d1}"; return "%vmovsd\t{%1, %0|%0, %1}"; case MODE_V4SF: @@ -3760,7 +3760,7 @@ { case MODE_SF: if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1])) - return "vmovss\t{%1, %0, %0|%0, %0, %1}"; + return "vmovss\t{%d1, %0|%0, %d1}"; return "%vmovss\t{%1, %0|%0, %1}"; case MODE_V16SF: @@ -15126,11 +15126,13 @@ (symbol_ref "false"))))]) (define_insn "*rcpsf2_sse" - [(set (match_operand:SF 0 "register_operand" "=x") - (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")] + [(set (match_operand:SF 0 "register_operand" "=x,x") + (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "x,m")] UNSPEC_RCP))] "TARGET_SSE && TARGET_SSE_MATH" - "%vrcpss\t{%1, %d0|%d0, %1}" + "@ + %vrcpss\t{%d1, %0|%0, %d1} + %vrcpss\t{%1, %d0|%d0, %1}" [(set_attr "type" "sse") (set_attr "atom_sse_attr" "rcp") (set_attr "btver2_sse_attr" "rcp") @@ -15428,11 +15430,13 @@ (set_attr "bdver1_decode" "direct")]) (define_insn "*rsqrtsf2_sse" - [(set (match_operand:SF 0 "register_operand" "=x") - (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")] + [(set (match_operand:SF 0 "register_operand" "=x,x") + (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "x,m")] UNSPEC_RSQRT))] "TARGET_SSE && TARGET_SSE_MATH" - "%vrsqrtss\t{%1, %d0|%d0, %1}" + "@ + %vrsqrtss\t{%d1, %0|%0, %d1} + %vrsqrtss\t{%1, %d0|%d0, %1}" [(set_attr "type" "sse") (set_attr "atom_sse_attr" "rcp") (set_attr "btver2_sse_attr" "rcp") @@ -15450,11 +15454,13 @@ }) (define_insn "*sqrt<mode>2_sse" - [(set (match_operand:MODEF 0 "register_operand" "=v") + [(set (match_operand:MODEF 0 "register_operand" "=v,v") (sqrt:MODEF - (match_operand:MODEF 1 "nonimmediate_operand" "vm")))] + (match_operand:MODEF 1 "nonimmediate_operand" "v,m")))] "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" - "%vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}" + "@ + %vsqrt<ssemodesuffix>\t{%d1, %0|%0, %d1} + %vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}" [(set_attr "type" "sse") (set_attr "atom_sse_attr" "sqrt") (set_attr "btver2_sse_attr" "sqrt") |