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authorJuzhe-Zhong <juzhe.zhong@rivai.ai>2023-09-01 07:10:00 +0800
committerPan Li <pan2.li@intel.com>2023-09-01 19:02:06 +0800
commit5f2098cce6c75117927fef317c714dd2088b0189 (patch)
tree59a4833aa0d74599edeaf7d3d20460a4c19db806
parentffbb19c6afc016f6dc001ad0f567d3216ff601b1 (diff)
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RISC-V: Enable VECT_COMPARE_COSTS by default
since we have added COST framework, we by default enable VECT_COMPARE_COSTS. Also, add 16/32/64 to provide more choices for COST comparison. This patch doesn't change any behavior from the current testsuite since we are using default COST model. gcc/ChangeLog: * config/riscv/riscv-v.cc (autovectorize_vector_modes): Enable VECT_COMPARE_COSTS by default.
-rw-r--r--gcc/config/riscv/riscv-v.cc9
1 files changed, 3 insertions, 6 deletions
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 6228ff3..c8ad96f 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2173,7 +2173,7 @@ autovectorize_vector_modes (vector_modes *modes, bool)
full vectors for wider elements.
- full_size / 8:
Try using 64-bit containers for all element types. */
- static const int rvv_factors[] = {1, 2, 4, 8};
+ static const int rvv_factors[] = {1, 2, 4, 8, 16, 32, 64};
for (unsigned int i = 0; i < sizeof (rvv_factors) / sizeof (int); i++)
{
poly_uint64 units;
@@ -2183,12 +2183,8 @@ autovectorize_vector_modes (vector_modes *modes, bool)
modes->safe_push (mode);
}
}
- unsigned int flag = 0;
if (TARGET_VECTOR_VLS)
{
- /* Enable VECT_COMPARE_COSTS between VLA modes VLS modes for scalable
- auto-vectorization. */
- flag |= VECT_COMPARE_COSTS;
/* Push all VLSmodes according to TARGET_MIN_VLEN. */
unsigned int i = 0;
unsigned int base_size = TARGET_MIN_VLEN * riscv_autovec_lmul / 8;
@@ -2201,7 +2197,8 @@ autovectorize_vector_modes (vector_modes *modes, bool)
size = base_size / (1U << i);
}
}
- return flag;
+ /* Enable LOOP_VINFO comparison in COST model. */
+ return VECT_COMPARE_COSTS;
}
/* If the given VECTOR_MODE is an RVV mode, first get the largest number