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| author | Maciej W. Rozycki <macro@embecosm.com> | 2022-02-08 12:14:58 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@embecosm.com> | 2022-02-08 12:14:58 +0000 |
| commit | 5e92fddad7719f2f2cdf55f73222c4978af38f35 (patch) | |
| tree | 6da4d71dbb0866510e5e779da21cbf4df6b5c19a | |
| parent | 3faeba72cf93bdbf0b42d6b1b65fd4f0794f9d2a (diff) | |
| download | gcc-5e92fddad7719f2f2cdf55f73222c4978af38f35.zip gcc-5e92fddad7719f2f2cdf55f73222c4978af38f35.tar.gz gcc-5e92fddad7719f2f2cdf55f73222c4978af38f35.tar.bz2 | |
doc: RISC-V: Document the `-misa-spec=' option
We have recently updated the default for the `-misa-spec=' option, yet
we still have not documented it nor its `--with-isa-spec=' counterpart
in the GCC manuals. Fix that.
gcc/
* doc/install.texi (Configuration): Document `--with-isa-spec='
RISC-V option.
* doc/invoke.texi (Option Summary): List `-misa-spec=' RISC-V
option.
(RISC-V Options): Document it.
| -rw-r--r-- | gcc/doc/install.texi | 14 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 17 |
2 files changed, 31 insertions, 0 deletions
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index deb9938..93eae1f 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -1594,6 +1594,20 @@ On certain targets this option sets the default stack clash protection guard size as a power of two in bytes. On AArch64 @var{size} is required to be either 12 (4KB) or 16 (64KB). +@item --with-isa-spec=@var{ISA-spec-string} +On RISC-V targets specify the default version of the RISC-V Unprivileged +(formerly User-Level) ISA specification to produce code conforming to. +The possibilities for @var{ISA-spec-string} are: +@table @code +@item 2.2 +Produce code conforming to version 2.2. +@item 20190608 +Produce code conforming to version 20190608. +@item 20191213 +Produce code conforming to version 20191213. +@end table +In the absence of this configuration option the default version is 20191213. + @item --enable-__cxa_atexit Define if you want to use __cxa_atexit, rather than atexit, to register C++ destructors for local statics and global objects. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8bd5293..ac97247 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1184,6 +1184,7 @@ See RS/6000 and PowerPC Options. -mabi=@var{ABI-string} @gol -mfdiv -mno-fdiv @gol -mdiv -mno-div @gol +-misa-spec=@var{ISA-spec-string} @gol -march=@var{ISA-string} @gol -mtune=@var{processor-string} @gol -mpreferred-stack-boundary=@var{num} @gol @@ -27633,6 +27634,22 @@ Do or don't use hardware instructions for integer division. This requires the M extension. The default is to use them if the specified architecture has these instructions. +@item -misa-spec=@var{ISA-spec-string} +@opindex misa-spec +Specify the version of the RISC-V Unprivileged (formerly User-Level) +ISA specification to produce code conforming to. The possibilities +for @var{ISA-spec-string} are: +@table @code +@item 2.2 +Produce code conforming to version 2.2. +@item 20190608 +Produce code conforming to version 20190608. +@item 20191213 +Produce code conforming to version 20191213. +@end table +The default is @option{-misa-spec=20191213} unless GCC has been configured +with @option{--with-isa-spec=} specifying a different default version. + @item -march=@var{ISA-string} @opindex march Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}). ISA strings must be |