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| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-01-13 11:49:45 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-01-13 11:49:45 +0000 |
| commit | 5ab67cdee6144cfca0705612a898f1940d4f3994 (patch) | |
| tree | cb4aaa8487f32f70aaaba5a83ef08b3b719ad5b7 | |
| parent | 6d75168146f73aa381dcee34b458d8f88ea8f95a (diff) | |
| download | gcc-5ab67cdee6144cfca0705612a898f1940d4f3994.zip gcc-5ab67cdee6144cfca0705612a898f1940d4f3994.tar.gz gcc-5ab67cdee6144cfca0705612a898f1940d4f3994.tar.bz2 | |
aarch64: Tighten condition on sve/sel* tests
Noticed while testing on a different machine that the sve/sel_*.c
tests require .variant_pcs support but don't test for it.
.variant_pcs post-dates SVE so there shouldn't be a need to test
for both.
gcc/testsuite/
* gcc.target/aarch64/sve/sel_1.c: Require aarch64_variant_pcs.
* gcc.target/aarch64/sve/sel_2.c: Likewise.
* gcc.target/aarch64/sve/sel_3.c: Likewise.
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/sel_1.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/sel_2.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/sel_3.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/sel_1.c b/gcc/testsuite/gcc.target/aarch64/sve/sel_1.c index 9c581c5..65208dd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/sel_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/sel_1.c @@ -1,4 +1,4 @@ -/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-do assemble { target aarch64_variant_pcs } } */ /* { dg-options "-O2 -msve-vector-bits=256 --save-temps" } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/sel_2.c b/gcc/testsuite/gcc.target/aarch64/sve/sel_2.c index 60aaa87..8087073 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/sel_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/sel_2.c @@ -1,4 +1,4 @@ -/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-do assemble { target aarch64_variant_pcs } } */ /* { dg-options "-O2 -msve-vector-bits=256 --save-temps" } */ /* { dg-final { check-function-bodies "**" "" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/sel_3.c b/gcc/testsuite/gcc.target/aarch64/sve/sel_3.c index 36ec15b..68f9d97 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/sel_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/sel_3.c @@ -1,4 +1,4 @@ -/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-do assemble { target aarch64_variant_pcs } } */ /* { dg-options "-O2 -msve-vector-bits=256 --save-temps" } */ /* { dg-final { check-function-bodies "**" "" } } */ |