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| author | Fei Gao <gaofei@eswincomputing.com> | 2023-12-10 13:39:30 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-12-10 13:41:01 -0700 |
| commit | 5a4faf915575c690a25f0522dccc5b8d82909f10 (patch) | |
| tree | 15237d529e1fe877057a0410c023c84d67b35d2e | |
| parent | b3aed459634654d295a1d00e6c149565ced7a9a2 (diff) | |
| download | gcc-5a4faf915575c690a25f0522dccc5b8d82909f10.zip gcc-5a4faf915575c690a25f0522dccc5b8d82909f10.tar.gz gcc-5a4faf915575c690a25f0522dccc5b8d82909f10.tar.bz2 | |
[PATCH 2/5] [ifcvt] optimize x=c ? (y shift_op z):y by RISC-V Zicond like insns
op=[ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT]
Conditional op, if zero
rd = (rc == 0) ? (rs1 op rs2) : rs1
-->
czero.nez rd, rs2, rc
op rd, rs1, rd
Conditional op, if non-zero
rd = (rc != 0) ? (rs1 op rs2) : rs1
-->
czero.eqz rd, rs2, rc
op rd, rs1, rd
gcc/ChangeLog:
* ifcvt.cc (noce_cond_zero_binary_op_supported): Add support for shift
like op.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond_ifcvt_opt.c: Add tests for shift like op.
Co-authored-by: Xiao Zeng<zengxiao@eswincomputing.com>
| -rw-r--r-- | gcc/ifcvt.cc | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c | 53 |
2 files changed, 56 insertions, 1 deletions
diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index e4eda1a..6ac91b8 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -2920,7 +2920,9 @@ noce_cond_zero_binary_op_supported (rtx op) { enum rtx_code opcode = GET_CODE (op); - if (opcode == PLUS || opcode == MINUS || opcode == IOR || opcode == XOR) + if (opcode == PLUS || opcode == MINUS || opcode == IOR || opcode == XOR + || opcode == ASHIFT || opcode == ASHIFTRT || opcode == LSHIFTRT + || opcode == ROTATE || opcode == ROTATERT) return true; return false; diff --git a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c index dcb21c1..efed199 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c +++ b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c @@ -562,5 +562,58 @@ test_XOR_eqz_x_2_reverse_bin_oprands (long x, long z, long c) return x; } +long +test_ShiftLeft_eqz (long x, long y, long z, long c) +{ + if (c) + x = y << z; + else + x = y; + return x; +} + +long +test_ShiftR_eqz (long x, long y, long z, long c) +{ + if (c) + x = y >> z; + else + x = y; + return x; +} + +unsigned long +test_ShiftR_logical_eqz (unsigned long x, unsigned long y, unsigned long z, + unsigned long c) +{ + if (c) + x = y >> z; + else + x = y; + return x; +} + +unsigned long +test_RotateL_eqz (unsigned long x, unsigned long y, unsigned long z, + unsigned long c) +{ + if (c) + x = (y << z) | (y >> (64 - z)); + else + x = y; + return x; +} + +unsigned long +test_RotateR_eqz (unsigned long x, unsigned long y, unsigned long z, + unsigned long c) +{ + if (c) + x = (y >> z) | (y << (64 - z)); + else + x = y; + return x; +} + /* { dg-final { scan-assembler-times {czero\.eqz} 28 } } */ /* { dg-final { scan-assembler-times {czero\.nez} 28 } } */ |