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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-11-07 23:18:59 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-11-10 09:31:38 +0800 |
| commit | 5a410860640f0fbd0a744dd89130d7d709a0ef07 (patch) | |
| tree | 36e9e5d3e2441636850de487b80fad8d8a24c4c8 | |
| parent | 1fa7dde8d680f28ed66db47309ed5e8f2789054d (diff) | |
| download | gcc-5a410860640f0fbd0a744dd89130d7d709a0ef07.zip gcc-5a410860640f0fbd0a744dd89130d7d709a0ef07.tar.gz gcc-5a410860640f0fbd0a744dd89130d7d709a0ef07.tar.bz2 | |
test: Fix FAIL of pr97428.c for RVV
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr97428.c: Add additional compile option for riscv.
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/pr97428.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.dg/vect/pr97428.c b/gcc/testsuite/gcc.dg/vect/pr97428.c index ad64160..60dd984 100644 --- a/gcc/testsuite/gcc.dg/vect/pr97428.c +++ b/gcc/testsuite/gcc.dg/vect/pr97428.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target vect_double } */ +/* { dg-additional-options "--param vect-epilogues-nomask=0" { target riscv*-*-* } } */ typedef struct { double re, im; } dcmlx_t; typedef struct { double re[4], im[4]; } dcmlx4_t; |