diff options
| author | Ian Bolton <ian.bolton@arm.com> | 2013-03-19 16:18:46 +0000 |
|---|---|---|
| committer | Ian Bolton <ibolton@gcc.gnu.org> | 2013-03-19 16:18:46 +0000 |
| commit | 5977a10d4a600792417e439d7bc67a514226a125 (patch) | |
| tree | 0f3fc449269c560c20846a632f40382c6c4a0bad | |
| parent | bd83ff2c6700863b92c59931c4ba4a1bef97a50f (diff) | |
| download | gcc-5977a10d4a600792417e439d7bc67a514226a125.zip gcc-5977a10d4a600792417e439d7bc67a514226a125.tar.gz gcc-5977a10d4a600792417e439d7bc67a514226a125.tar.bz2 | |
AArch64 backend support for ROR instruction.
From-SVN: r196796
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 28 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 |
3 files changed, 37 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4b2d216..d55999e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2013-03-19 Ian Bolton <ian.bolton@arm.com> + * config/aarch64/aarch64.md (*ror<mode>3_insn): New pattern. + (*rorsi3_insn_uxtw): Likewise. + +2013-03-19 Ian Bolton <ian.bolton@arm.com> + * config/aarch64/aarch64.md (*extr<mode>5_insn): New pattern. (*extrsi5_insn_uxtw): Likewise. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 8fc86d4..4358b44 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2731,6 +2731,34 @@ (set_attr "mode" "SI")] ) +(define_insn "*ror<mode>3_insn" + [(set (match_operand:GPI 0 "register_operand" "=r") + (rotate:GPI (match_operand:GPI 1 "register_operand" "r") + (match_operand 2 "const_int_operand" "n")))] + "UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" +{ + operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2])); + return "ror\\t%<w>0, %<w>1, %3"; +} + [(set_attr "v8type" "shift") + (set_attr "mode" "<MODE>")] +) + +;; zero_extend version of the above +(define_insn "*rorsi3_insn_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (rotate:SI (match_operand:SI 1 "register_operand" "r") + (match_operand 2 "const_int_operand" "n"))))] + "UINTVAL (operands[2]) < 32" +{ + operands[3] = GEN_INT (32 - UINTVAL (operands[2])); + return "ror\\t%w0, %w1, %3"; +} + [(set_attr "v8type" "shift") + (set_attr "mode" "SI")] +) + (define_insn "*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>" [(set (match_operand:GPI 0 "register_operand" "=r") (ANY_EXTEND:GPI diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fa69025..e198a6e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2013-03-19 Ian Bolton <ian.bolton@arm.com> + * gcc.target/aarch64/ror.c: New test. + +2013-03-19 Ian Bolton <ian.bolton@arm.com> + * gcc.target/aarch64/extr.c: New test. 2013-03-19 Richard Biener <rguenther@suse.de> |