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authorJim Wilson <wilson@cygnus.com>1997-08-29 15:19:58 +0000
committerJeff Law <law@gcc.gnu.org>1997-08-29 09:19:58 -0600
commit575833386fa593c86f362bc385b89ee410895328 (patch)
treea6431ac65bced6119c4b53601cb7fdf5967fea9b
parent4f91a0f87a988b3a4efbcdabbaa9e92a42676e69 (diff)
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m68k.md (iorsi_zexthi_ashl16): Disable.
* m68k/m68k.md (iorsi_zexthi_ashl16): Disable. Fixes m68k codegen problem. From-SVN: r14996
-rw-r--r--gcc/ChangeLog4
-rw-r--r--gcc/config/m68k/m68k.md11
2 files changed, 14 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index aba37c0..d7c2e50 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+Thu Aug 28 15:14:46 1997 Jim Wilson <wilson@cygnus.com>
+
+ * m68k/m68k.md (iorsi_zexthi_ashl16): Disable.
+
1997-08-27 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* Makefile.in (config.status): Depend on version.c
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 456b277..2413c64 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -3733,12 +3733,21 @@
;; On all 68k models, this makes faster code in a special case.
;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
+;; ??? This pattern can not work as written, because it fails if operand 0
+;; and operand 1 are the same register. This can happen for alternative 1.
+;; This will still fail even if an early clobber is added to the output
+;; for alternative 1. This is because reload may satisfy the matching
+;; constraint by forcing the output to use exactly the same register as
+;; operand 2, without noticing that this then causes a conflict with operand 1.
+;; Possible fix: check for operand 0/1 overlap, and emit correct but slower
+;; code. This should be rare if the early clobber is added.
+
(define_insn "iorsi_zexthi_ashl16"
[(set (match_operand:SI 0 "general_operand" "=&d,d")
(ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
(ashift:SI (match_operand:SI 2 "general_operand" "o,0")
(const_int 16))))]
- ""
+ "0"
"*
{
CC_STATUS_INIT;