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| author | Kito Cheng <kito.cheng@sifive.com> | 2021-03-22 16:32:45 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2021-03-22 17:47:02 +0800 |
| commit | 540dace2ed3949571f2ce6cb007354e69bda0cb2 (patch) | |
| tree | 747538b09e16a422eb3dc19526de11af94cc82f1 | |
| parent | 0e792ee11aa6ebb6f61e9ed33eb06e260f0ec703 (diff) | |
| download | gcc-540dace2ed3949571f2ce6cb007354e69bda0cb2.zip gcc-540dace2ed3949571f2ce6cb007354e69bda0cb2.tar.gz gcc-540dace2ed3949571f2ce6cb007354e69bda0cb2.tar.bz2 | |
PR target/99702: Check RTL type before get value
gcc/ChangeLog:
PR target/99702
* config/riscv/riscv.c (riscv_expand_block_move): Get RTL value
after type checking.
gcc/testsuite/ChangeLog:
PR target/99702
* gcc.target/riscv/pr99702.c: New.
| -rw-r--r-- | gcc/config/riscv/riscv.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/pr99702.c | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 96fc0c0..de8308c 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3259,9 +3259,9 @@ riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length, bool riscv_expand_block_move (rtx dest, rtx src, rtx length) { - unsigned HOST_WIDE_INT hwi_length = UINTVAL (length); if (CONST_INT_P (length)) { + unsigned HOST_WIDE_INT hwi_length = UINTVAL (length); unsigned HOST_WIDE_INT factor, align; align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD); diff --git a/gcc/testsuite/gcc.target/riscv/pr99702.c b/gcc/testsuite/gcc.target/riscv/pr99702.c new file mode 100644 index 0000000..a28724c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr99702.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ +char n; +void *i, *j; +void foo(void) { + __builtin_memcpy(i, j, n); +} |