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| author | Eric Botcazou <ebotcazou@libertysurf.fr> | 2003-06-05 10:36:53 +0200 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2003-06-05 08:36:53 +0000 |
| commit | 53e5f173239cede18bf6c52642d97c38b941467a (patch) | |
| tree | 1306630abc3de92168eb9cc801fc87dca7f8883d | |
| parent | c6cc7e13f4226edc7078d610fa18e55676e0a4f6 (diff) | |
| download | gcc-53e5f173239cede18bf6c52642d97c38b941467a.zip gcc-53e5f173239cede18bf6c52642d97c38b941467a.tar.gz gcc-53e5f173239cede18bf6c52642d97c38b941467a.tar.bz2 | |
md.texi (Machine Constraints): Correct the meaning of constraints related to floating-point registers on SPARC.
* doc/md.texi (Machine Constraints): Correct the meaning of
constraints related to floating-point registers on SPARC.
From-SVN: r67481
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 17 |
2 files changed, 14 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8697fa6..b639d17 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,9 @@ 2003-06-05 Eric Botcazou <ebotcazou@libertysurf.fr> + + * doc/md.texi (Machine Constraints): Correct the meaning of + constraints related to floating-point registers on SPARC. + +2003-06-05 Eric Botcazou <ebotcazou@libertysurf.fr> Paolo Bonzini <bonzini@gnu.org> PR target/10663 diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 8b319cf..314ecf0 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2015,23 +2015,24 @@ Constants in the range @minus{}8 to 2 @item SPARC---@file{sparc.h} @table @code @item f -Floating-point register that can hold 32- or 64-bit values. +Floating-point register on the SPARC-V8 architecture and +lower floating-point register on the SPARC-V9 architecture. @item e -Floating-point register that can hold 64- or 128-bit values. +Floating-point register. It is equivalent to @samp{f} on the +SPARC-V8 architecture and contains both lower and upper +floating-point registers on the SPARC-V9 architecture. @item c Floating-point condition code register. @item d -Floating-point register that can hold 32- or 64-bit values. -It is only valid on the SPARC-V9 architecture when the Visual -Instructions Set is available. +Lower floating-point register. It is only valid on the SPARC-V9 +architecture when the Visual Instruction Set is available. @item b -Floating-point register that can hold 64- or 128-bit values. -It is only valid on the SPARC-V9 architecture when the Visual -Instructions Set is available. +Floating-point register. It is only valid on the SPARC-V9 architecture +when the Visual Instruction Set is available. @item h 64-bit global or out register for the SPARC-V8+ architecture. |