RISC-V: Report Sorry when users enable RVV in big-endian mode [PR113404]

As PR113404 mentioned: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113404

We have ICE when we enable RVV in big-endian mode:

during RTL pass: expand
a-float-point-dynamic-frm-66.i:2:14: internal compiler error: in to_constant, at poly-int.h:588
0xab4c2c poly_int<2u, unsigned short>::to_constant() const
        /repo/gcc-trunk/gcc/poly-int.h:588
0xab4de1 poly_int<2u, unsigned short>::to_constant() const
        /repo/gcc-trunk/gcc/tree.h:4055
0xab4de1 default_function_arg_padding(machine_mode, tree_node const*)
        /repo/gcc-trunk/gcc/targhooks.cc:844
0x12e2327 locate_and_pad_parm(machine_mode, tree_node*, int, int, int, tree_node*, args_size*, locate_and_pad_arg_data*)
        /repo/gcc-trunk/gcc/function.cc:4061
0x12e2aca assign_parm_find_entry_rtl
        /repo/gcc-trunk/gcc/function.cc:2614
0x12e2c89 assign_parms
        /repo/gcc-trunk/gcc/function.cc:3693
0x12e59df expand_function_start(tree_node*)
        /repo/gcc-trunk/gcc/function.cc:5152
0x112fafb execute
        /repo/gcc-trunk/gcc/cfgexpand.cc:6739

Report users that we don't support RVV in big-endian mode for the following reasons:
1. big-endian in RISC-V is pretty rare case.
2. We didn't test RVV in big-endian and we don't have enough time to test it since it's stage 4 now.

Naive disallow RVV in big-endian.

Tested no regression, ok for trunk ?

gcc/ChangeLog:

	PR target/113404
	* config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
	for RVV in big-endian mode.

gcc/testsuite/ChangeLog:

	PR target/113404
	* gcc.target/riscv/rvv/base/big_endian-1.c: New test.
	* gcc.target/riscv/rvv/base/big_endian-2.c: New test.

3 files changed, 15 insertions, 0 deletions

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 89caf15..41626fa 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8787,6 +8787,11 @@ riscv_override_options_internal (struct gcc_options *opts)
     sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
 	   "'V' Extension");
 
+  /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
+     big-endian after finishing full coverage testing.  */
+  if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
+    sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
+
   /* Convert -march to a chunks count.  */
   riscv_vector_chunks = riscv_convert_vector_bits (opts);
 }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-1.c
new file mode 100644
index 0000000..9eaf7ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-1.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mbig-endian -O3" } */
+
+#pragma riscv intrinsic "vector"
+vfloat32m1_t foo (vfloat32m1_t) {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC cannot support RVV in big-endian mode" }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c
new file mode 100644
index 0000000..86cf583
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32x -mabi=lp64d -mbig-endian -O3" } */
+
+#pragma riscv intrinsic "vector"
+vint32m1_t foo (vint32m1_t) {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC cannot support RVV in big-endian mode" }