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author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-09-05 16:47:25 +0800 |
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committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-09-05 17:04:55 +0800 |
commit | 509c10a62546b9b3430040e455b7258322a024e6 (patch) | |
tree | 9f953277970cc719d1ccc8187864e7a7bf8d3eb1 | |
parent | 8451fbd56871267e8c1cd781db6d8f02e826f66c (diff) | |
download | gcc-509c10a62546b9b3430040e455b7258322a024e6.zip gcc-509c10a62546b9b3430040e455b7258322a024e6.tar.gz gcc-509c10a62546b9b3430040e455b7258322a024e6.tar.bz2 |
RISC-V: Export functions as global extern preparing for dynamic LMUL patch use
Notice those functions need to be use by COST model for dynamic LMUL use.
Extract as a single patch and committed.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (lookup_vector_type_attribute): Export global.
(get_all_predecessors): New function.
(get_all_successors): Ditto.
* config/riscv/riscv-v.cc (get_all_predecessors): Ditto.
(get_all_successors): Ditto.
* config/riscv/riscv-vector-builtins.cc (sizeless_type_p): Export global.
* config/riscv/riscv-vsetvl.cc (get_all_predecessors): Remove it.
-rw-r--r-- | gcc/config/riscv/riscv-protos.h | 3 | ||||
-rw-r--r-- | gcc/config/riscv/riscv-v.cc | 48 | ||||
-rw-r--r-- | gcc/config/riscv/riscv-vector-builtins.cc | 2 | ||||
-rw-r--r-- | gcc/config/riscv/riscv-vsetvl.cc | 25 |
4 files changed, 52 insertions, 26 deletions
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index dd7aa36..0b4dd45 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -365,6 +365,7 @@ enum avl_type /* Routines implemented in riscv-vector-builtins.cc. */ void init_builtins (void); const char *mangle_builtin_type (const_tree); +tree lookup_vector_type_attribute (const_tree); #ifdef GCC_TARGET_H bool verify_type_context (location_t, type_context_kind, const_tree, bool); bool expand_vec_perm_const (machine_mode, machine_mode, rtx, rtx, rtx, @@ -493,6 +494,8 @@ enum floating_point_rounding_mode get_frm_mode (rtx); opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode, poly_uint64); unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool); +hash_set<basic_block> get_all_predecessors (basic_block); +hash_set<basic_block> get_all_successors (basic_block); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 6394548..1ca3f1d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3387,4 +3387,52 @@ expand_fold_extract_last (rtx *ops) emit_label (end_label); } +hash_set<basic_block> +get_all_predecessors (basic_block bb) +{ + hash_set<basic_block> blocks; + auto_vec<basic_block> work_list; + hash_set<basic_block> visited_list; + work_list.safe_push (bb); + + while (!work_list.is_empty ()) + { + basic_block new_bb = work_list.pop (); + visited_list.add (new_bb); + edge e; + edge_iterator ei; + FOR_EACH_EDGE (e, ei, new_bb->preds) + { + if (!visited_list.contains (e->src)) + work_list.safe_push (e->src); + blocks.add (e->src); + } + } + return blocks; +} + +hash_set<basic_block> +get_all_successors (basic_block bb) +{ + hash_set<basic_block> blocks; + auto_vec<basic_block> work_list; + hash_set<basic_block> visited_list; + work_list.safe_push (bb); + + while (!work_list.is_empty ()) + { + basic_block new_bb = work_list.pop (); + visited_list.add (new_bb); + edge e; + edge_iterator ei; + FOR_EACH_EDGE (e, ei, new_bb->succs) + { + if (!visited_list.contains (e->dest)) + work_list.safe_push (e->dest); + blocks.add (e->dest); + } + } + return blocks; +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 4a7eb47..01a8d71 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -2671,7 +2671,7 @@ sizeless_type_p (const_tree type) /* If TYPE is an ABI-defined RVV type, return its attribute descriptor, otherwise return null. */ -static tree +tree lookup_vector_type_attribute (const_tree type) { if (type == error_mark_node) diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index a81bb53..e7e5c14 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -521,31 +521,6 @@ get_same_bb_set (hash_set<set_info *> &sets, const basic_block cfg_bb) return nullptr; } -/* Recursively find all predecessor blocks for cfg_bb. */ -static hash_set<basic_block> -get_all_predecessors (basic_block cfg_bb) -{ - hash_set<basic_block> blocks; - auto_vec<basic_block> work_list; - hash_set<basic_block> visited_list; - work_list.safe_push (cfg_bb); - - while (!work_list.is_empty ()) - { - basic_block new_cfg_bb = work_list.pop (); - visited_list.add (new_cfg_bb); - edge e; - edge_iterator ei; - FOR_EACH_EDGE (e, ei, new_cfg_bb->preds) - { - if (!visited_list.contains (e->src)) - work_list.safe_push (e->src); - blocks.add (e->src); - } - } - return blocks; -} - /* Helper function to get SEW operand. We always have SEW value for all RVV instructions that have VTYPE OP. */ static uint8_t |