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| author | Zhenqiang Chen <zhenqiang.chen@arm.com> | 2014-09-24 07:00:55 +0000 |
|---|---|---|
| committer | Zhenqiang Chen <zqchen@gcc.gnu.org> | 2014-09-24 07:00:55 +0000 |
| commit | 4ef20c29a3e67224a3311ef4f620b815d4fceaeb (patch) | |
| tree | a51e3c8ae714c6784a3022ded163b248ac0c849a | |
| parent | f704cf4c32a824de157757f9c4926e24d8904e80 (diff) | |
| download | gcc-4ef20c29a3e67224a3311ef4f620b815d4fceaeb.zip gcc-4ef20c29a3e67224a3311ef4f620b815d4fceaeb.tar.gz gcc-4ef20c29a3e67224a3311ef4f620b815d4fceaeb.tar.bz2 | |
re PR rtl-optimization/63210 (ira does not select the best register compared with gcc 4.8 for ARM THUMB1)
ChangeLog:
2014-09-24 Zhenqiang Chen <zhenqiang.chen@arm.com>
PR rtl-optimization/63210
* ira-color.c (assign_hard_reg): Ignore conflict cost if the
HARD_REGNO is not availabe for CONFLICT_A.
testsuite/ChangeLog:
2014-09-24 Zhenqiang Chen <zhenqiang.chen@arm.com>
* gcc.target/arm/pr63210.c: New test.
From-SVN: r215540
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/ira-color.c | 8 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr63210.c | 12 |
4 files changed, 29 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a0de60b..10dbc52 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2014-09-24 Zhenqiang Chen <zhenqiang.chen@arm.com> + + PR rtl-optimization/63210 + * ira-color.c (assign_hard_reg): Ignore conflict cost if the + HARD_REGNO is not available for CONFLICT_A. + 2014-09-23 Andi Kleen <ak@linux.intel.com> * cgraph.h (symtab_node): Add no_reorder attribute. diff --git a/gcc/ira-color.c b/gcc/ira-color.c index 1042eaa..841d0d1 100644 --- a/gcc/ira-color.c +++ b/gcc/ira-color.c @@ -1709,6 +1709,7 @@ assign_hard_reg (ira_allocno_t a, bool retry_p) { ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj); enum reg_class conflict_aclass; + allocno_color_data_t data = ALLOCNO_COLOR_DATA (conflict_a); /* Reload can give another class so we need to check all allocnos. */ @@ -1780,7 +1781,12 @@ assign_hard_reg (ira_allocno_t a, bool retry_p) hard_regno = ira_class_hard_regs[aclass][j]; ira_assert (hard_regno >= 0); k = ira_class_hard_reg_index[conflict_aclass][hard_regno]; - if (k < 0) + if (k < 0 + /* If HARD_REGNO is not available for CONFLICT_A, + the conflict would be ignored, since HARD_REGNO + will never be assigned to CONFLICT_A. */ + || !TEST_HARD_REG_BIT (data->profitable_hard_regs, + hard_regno)) continue; full_costs[j] -= conflict_costs[k]; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2fb28b9..a3f51b3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2014-09-24 Zhenqiang Chen <zhenqiang.chen@arm.com> + + * gcc.target/arm/pr63210.c: New test. + 2014-09-23 Andi Kleen <ak@linux.intel.com> * gcc.dg/noreorder.c: New test. diff --git a/gcc/testsuite/gcc.target/arm/pr63210.c b/gcc/testsuite/gcc.target/arm/pr63210.c new file mode 100644 index 0000000..c3ae928 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr63210.c @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-mthumb -Os " } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +int foo1 (int c); +int foo2 (int c); + +int test (int c) +{ + return (foo1 (c) || foo2 (c)); +} +/* { dg-final { object-size text <= 28 } } */ |