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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2017-06-21 21:08:40 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2017-06-21 21:08:40 +0000 |
| commit | 4ded86690e9fd3c71e1ff47beea31079ad8a7b4f (patch) | |
| tree | db486df00c7369163b2fa40b02af77456d04dea5 | |
| parent | ac135a731d319ec86562f7ff4a42453df3078836 (diff) | |
| download | gcc-4ded86690e9fd3c71e1ff47beea31079ad8a7b4f.zip gcc-4ded86690e9fd3c71e1ff47beea31079ad8a7b4f.tar.gz gcc-4ded86690e9fd3c71e1ff47beea31079ad8a7b4f.tar.bz2 | |
re PR target/80510 (Optimize Power7/power8 Altivec load/stores)
2017-06-21 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80510
* gcc.target/powerpc/pr80510-1.c: Restrict test to 64-bit until
32-bit support is added. Change ITYPE size to 64-bit integer.
* gcc.target/powerpc/pr80510-2.c: Likewise.
From-SVN: r249470
| -rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/pr80510-1.c | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/pr80510-2.c | 8 |
3 files changed, 17 insertions, 6 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0239d5a..fa14c61 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2017-06-21 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/80510 + * gcc.target/powerpc/pr80510-1.c: Restrict test to 64-bit until + 32-bit support is added. Change ITYPE size to 64-bit integer. + * gcc.target/powerpc/pr80510-2.c: Likewise. + 2017-06-21 Jakub Jelinek <jakub@redhat.com> PR c++/81154 diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c index 7024f3b..d832e92 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ @@ -6,7 +6,9 @@ /* Make sure that STXSDX is generated for double scalars in Altivec registers on power7 instead of moving the value to a FPR register and doing a X-FORM - store. */ + store. + + 32-bit currently does not have support for STXSDX in the mov{df,dd} patterns. */ #ifndef TYPE #define TYPE double @@ -21,7 +23,7 @@ #endif #ifndef ITYPE -#define ITYPE long +#define ITYPE __INT64_TYPE__ #endif #ifdef DO_CALL diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c index 18dc356..83a186b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ @@ -6,7 +6,9 @@ /* Make sure that STXSSPX is generated for float scalars in Altivec registers on power7 instead of moving the value to a FPR register and doing a X-FORM - store. */ + store. + + 32-bit currently does not have support for STXSSPX in the mov{sf,sd} patterns. */ #ifndef TYPE #define TYPE float @@ -21,7 +23,7 @@ #endif #ifndef ITYPE -#define ITYPE long +#define ITYPE __INT64_TYPE__ #endif #ifdef DO_CALL |