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| author | Uros Bizjak <ubizjak@gmail.com> | 2023-11-05 20:53:02 +0100 |
|---|---|---|
| committer | Uros Bizjak <ubizjak@gmail.com> | 2023-11-05 20:55:42 +0100 |
| commit | 4dbb14c26dafe70ee4bef5fdf8df39d001dd56f1 (patch) | |
| tree | 281a0b44cbd71e814e60986d352cfe47a0c63b13 | |
| parent | 2d55ed2b8a754d7279cd002941f7cb481f0fd133 (diff) | |
| download | gcc-4dbb14c26dafe70ee4bef5fdf8df39d001dd56f1.zip gcc-4dbb14c26dafe70ee4bef5fdf8df39d001dd56f1.tar.gz gcc-4dbb14c26dafe70ee4bef5fdf8df39d001dd56f1.tar.bz2 | |
i386: Add LEGACY_INDEX_REG register class.
Also rename LEGACY_REGS to LEGACY_GENERAL_REGS.
gcc/ChangeLog:
* config/i386/i386.h (enum reg_class): Add LEGACY_INDEX_REGS.
Rename LEGACY_REGS to LEGACY_GENERAL_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
* config/i386/constraints.md ("R"): Update for rename.
| -rw-r--r-- | gcc/config/i386/constraints.md | 2 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 36 |
2 files changed, 22 insertions, 16 deletions
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index dc91bd9..f627574 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -23,7 +23,7 @@ ;; Integer register constraints. ;; It is not necessary to define 'r' here. -(define_register_constraint "R" "LEGACY_REGS" +(define_register_constraint "R" "LEGACY_GENERAL_REGS" "Legacy register---the eight integer registers available on all i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, @code{si}, @code{di}, @code{bp}, @code{sp}).") diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index a56367a..0370747 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1307,12 +1307,16 @@ enum reg_class Q_REGS, /* %eax %ebx %ecx %edx */ NON_Q_REGS, /* %esi %edi %ebp %esp */ TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */ - INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ - LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ + LEGACY_GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ + LEGACY_INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */ + INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp + %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 + %r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23 + %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */ GENERAL_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ INDEX_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp @@ -1376,9 +1380,10 @@ enum reg_class "CLOBBERED_REGS", \ "Q_REGS", "NON_Q_REGS", \ "TLS_GOTBASE_REGS", \ - "INDEX_REGS", \ - "LEGACY_REGS", \ + "LEGACY_GENERAL_REGS", \ + "LEGACY_INDEX_REGS", \ "GENERAL_REGS", \ + "INDEX_REGS", \ "GENERAL_GPR16", \ "INDEX_GPR16", \ "FP_TOP_REG", "FP_SECOND_REG", \ @@ -1416,11 +1421,12 @@ enum reg_class { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \ { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \ - { 0x7f, 0xff0, 0xffff000 }, /* INDEX_REGS */ \ - { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ - { 0x900ff, 0xff0, 0xffff000 }, /* GENERAL_REGS */ \ + { 0x900ff, 0x0, 0x0 }, /* LEGACY_GENERAL_REGS */ \ + { 0x7f, 0x0, 0x0 }, /* LEGACY_INDEX_REGS */ \ + { 0x900ff, 0xff0, 0xffff000 }, /* GENERAL_REGS */ \ + { 0x7f, 0xff0, 0xffff000 }, /* INDEX_REGS */ \ { 0x900ff, 0xff0, 0x0 }, /* GENERAL_GPR16 */ \ - { 0x0007f, 0xff0, 0x0 }, /* INDEX_GPR16 */ \ + { 0x7f, 0xff0, 0x0 }, /* INDEX_GPR16 */ \ { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ @@ -1430,13 +1436,13 @@ enum reg_class { 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \ { 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \ { 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \ - { 0x9ffff, 0xff0, 0xffff000 }, /* FLOAT_INT_REGS */ \ - { 0xff900ff, 0xfffffff0, 0xffff00f }, /* INT_SSE_REGS */ \ - { 0xff9ffff, 0xfffffff0, 0xffff00f }, /* FLOAT_INT_SSE_REGS */ \ - { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \ - { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \ - { 0x900ff, 0xff0, 0xffffff0 }, /* INT_MASK_REGS */ \ -{ 0xffffffff, 0xffffffff, 0xfffffff } /* ALL_REGS */ \ + { 0x9ffff, 0xff0, 0xffff000 }, /* FLOAT_INT_REGS */ \ + { 0xff900ff, 0xfffffff0, 0xffff00f }, /* INT_SSE_REGS */ \ + { 0xff9ffff, 0xfffffff0, 0xffff00f }, /* FLOAT_INT_SSE_REGS */ \ + { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \ + { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \ + { 0x900ff, 0xff0, 0xffffff0 }, /* INT_MASK_REGS */ \ +{ 0xffffffff, 0xffffffff, 0xfffffff } /* ALL_REGS */ \ } /* The same information, inverted: |