diff options
| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-09-11 11:22:26 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-09-11 11:25:51 +0800 |
| commit | 4ab2520ec424fa097ec839f2cde33522b220e93a (patch) | |
| tree | f8d3d11e27308e970822246fae7e004d1ac7d366 | |
| parent | 190cf0ce8f4c141ac5b42d53b9ddeba367495333 (diff) | |
| download | gcc-4ab2520ec424fa097ec839f2cde33522b220e93a.zip gcc-4ab2520ec424fa097ec839f2cde33522b220e93a.tar.gz gcc-4ab2520ec424fa097ec839f2cde33522b220e93a.tar.bz2 | |
RISC-V: Add missing VLS mask bool mode reg -> reg patterns
Committed.
gcc/ChangeLog:
* config/riscv/autovec-vls.md (*mov<mode>_vls): New pattern.
* config/riscv/vector-iterators.md: New iterator
| -rw-r--r-- | gcc/config/riscv/autovec-vls.md | 8 | ||||
| -rw-r--r-- | gcc/config/riscv/vector-iterators.md | 15 |
2 files changed, 23 insertions, 0 deletions
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index d208b41..6f48f7d 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -148,6 +148,14 @@ [(set_attr "type" "vmov") (set_attr "mode" "<MODE>")]) +(define_insn "*mov<mode>_vls" + [(set (match_operand:VLSB 0 "register_operand" "=vr") + (match_operand:VLSB 1 "register_operand" " vr"))] + "TARGET_VECTOR" + "vmv1r.v\t%0,%1" + [(set_attr "type" "vmov") + (set_attr "mode" "<MODE>")]) + (define_expand "movmisalign<mode>" [(set (match_operand:VLS 0 "nonimmediate_operand") (match_operand:VLS 1 "general_operand"))] diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a98ed9f..5694c0c 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -2425,6 +2425,21 @@ (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")]) +(define_mode_iterator VLSB [ + (V1BI "TARGET_VECTOR_VLS") + (V2BI "TARGET_VECTOR_VLS") + (V4BI "TARGET_VECTOR_VLS") + (V8BI "TARGET_VECTOR_VLS") + (V16BI "TARGET_VECTOR_VLS") + (V32BI "TARGET_VECTOR_VLS") + (V64BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64") + (V128BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128") + (V256BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256") + (V512BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512") + (V1024BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024") + (V2048BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048") + (V4096BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")]) + ;; VLS modes that has NUNITS < 32. (define_mode_iterator VLS_AVL_IMM [ (V1QI "TARGET_VECTOR_VLS") |