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| author | Jie Zhang <jie.zhang@analog.com> | 2007-08-29 09:35:52 +0000 |
|---|---|---|
| committer | Jie Zhang <jiez@gcc.gnu.org> | 2007-08-29 09:35:52 +0000 |
| commit | 48ccf0127ff6a5266a514f04c9c7827adcc56f19 (patch) | |
| tree | 494207f7316b1c330d532d7887cfa20b74f942ef | |
| parent | cc728da9c5b5311afc24b51845b893aeb8466bd0 (diff) | |
| download | gcc-48ccf0127ff6a5266a514f04c9c7827adcc56f19.zip gcc-48ccf0127ff6a5266a514f04c9c7827adcc56f19.tar.gz gcc-48ccf0127ff6a5266a514f04c9c7827adcc56f19.tar.bz2 | |
bfin.c (bfin_expand_builtin): Fix the argument order of __builtin_bfin_cmplx_mac and __builtin_bfin_cmplx_msu.
* config/bfin/bfin.c (bfin_expand_builtin): Fix the argument
order of __builtin_bfin_cmplx_mac and __builtin_bfin_cmplx_msu.
From-SVN: r127891
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/bfin/bfin.c | 12 |
2 files changed, 11 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4ffc94a..6e32ade 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2007-08-29 Jie Zhang <jie.zhang@analog.com> + * config/bfin/bfin.c (bfin_expand_builtin): Fix the argument + order of __builtin_bfin_cmplx_mac and __builtin_bfin_cmplx_msu. + +2007-08-29 Jie Zhang <jie.zhang@analog.com> + Revert 2007-08-29 Jie Zhang <jie.zhang@analog.com> * config/bfin/bfin.md (composev2hi): Put operands into vector diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index c97f3a7e..7b2f988 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -5411,25 +5411,25 @@ bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, || GET_MODE (target) != V2HImode || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode)) target = gen_reg_rtx (tmode); - if (! register_operand (op0, GET_MODE (op0))) - op0 = copy_to_mode_reg (GET_MODE (op0), op0); if (! register_operand (op1, GET_MODE (op1))) op1 = copy_to_mode_reg (GET_MODE (op1), op1); + if (! register_operand (op2, GET_MODE (op2))) + op2 = copy_to_mode_reg (GET_MODE (op2), op2); tmp1 = gen_reg_rtx (SImode); tmp2 = gen_reg_rtx (SImode); - emit_insn (gen_ashlsi3 (tmp1, gen_lowpart (SImode, op2), GEN_INT (16))); - emit_move_insn (tmp2, gen_lowpart (SImode, op2)); + emit_insn (gen_ashlsi3 (tmp1, gen_lowpart (SImode, op0), GEN_INT (16))); + emit_move_insn (tmp2, gen_lowpart (SImode, op0)); emit_insn (gen_movstricthi_1 (gen_lowpart (HImode, tmp2), const0_rtx)); emit_insn (gen_load_accumulator_pair (accvec, tmp1, tmp2)); - emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op0, op1, const0_rtx, + emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op1, op2, const0_rtx, const0_rtx, const0_rtx, const1_rtx, accvec, const0_rtx, const0_rtx, GEN_INT (MACFLAG_W32))); tmp1 = (fcode == BFIN_BUILTIN_CPLX_MAC_16 ? const1_rtx : const0_rtx); tmp2 = (fcode == BFIN_BUILTIN_CPLX_MAC_16 ? const0_rtx : const1_rtx); - emit_insn (gen_flag_macv2hi_parts (target, op0, op1, const1_rtx, + emit_insn (gen_flag_macv2hi_parts (target, op1, op2, const1_rtx, const1_rtx, const1_rtx, const0_rtx, accvec, tmp1, tmp2, GEN_INT (MACFLAG_NONE), accvec)); |