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| author | zhongjuzhe <juzhe.zhong@rivai.ai> | 2022-08-30 10:57:42 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-09-01 09:33:35 +0800 |
| commit | 45f1287268200ffd551faca83d5e819b279ade9f (patch) | |
| tree | 215c90efaf1153ddf290bdf5db67049ce0f38dc7 | |
| parent | e9f827d79102001d5f0593f0f9e01ab72b2aec9a (diff) | |
| download | gcc-45f1287268200ffd551faca83d5e819b279ade9f.zip gcc-45f1287268200ffd551faca83d5e819b279ade9f.tar.gz gcc-45f1287268200ffd551faca83d5e819b279ade9f.tar.bz2 | |
RISC-V: Fix comment in riscv.h
gcc/ChangeLog:
* config/riscv/riscv.h (enum reg_class): Change vype to vtype.
| -rw-r--r-- | gcc/config/riscv/riscv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 29582f7..3ee5a93 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -462,7 +462,7 @@ enum reg_class FP_REGS, /* floating-point registers */ FRAME_REGS, /* arg pointer and frame pointer */ VL_REGS, /* vl register */ - VTYPE_REGS, /* vype register */ + VTYPE_REGS, /* vtype register */ VM_REGS, /* v0.t registers */ VD_REGS, /* vector registers except v0.t */ V_REGS, /* vector registers */ |