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authorAndrew Stubbs <ams@codesourcery.com>2023-03-17 11:04:12 +0000
committerAndrew Stubbs <ams@codesourcery.com>2023-03-23 11:00:54 +0000
commit3b97715af0e848ef8703ac04665bde562b2ac159 (patch)
tree84c028c9f97b7caa87781b54eb2021ba6be108bc
parentdb80ccd34365c14e529111c94b93d3fb201b6eef (diff)
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amdgcn: Fix register size bug
Fix an issue in which "vectors" of duplicate entries placed in scalar registers caused the following 63 registers to be marked live, for the purpose of prologue generation, which resulted in stack corruption. gcc/ChangeLog: * config/gcn/gcn.cc (gcn_class_max_nregs): Handle vectors in SGPRs. (move_callee_saved_registers): Detect the bug condition early.
-rw-r--r--gcc/config/gcn/gcn.cc13
1 files changed, 13 insertions, 0 deletions
diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc
index 5bf88e9..a7d278c 100644
--- a/gcc/config/gcn/gcn.cc
+++ b/gcc/config/gcn/gcn.cc
@@ -492,6 +492,15 @@ gcn_class_max_nregs (reg_class_t rclass, machine_mode mode)
}
else if (rclass == VCC_CONDITIONAL_REG && mode == BImode)
return 2;
+
+ /* Vector modes in SGPRs are not supposed to happen (disallowed by
+ gcn_hard_regno_mode_ok), but there are some patterns that have an "Sv"
+ constraint and are used by splitters, post-reload.
+ This ensures that we don't accidentally mark the following 63 scalar
+ registers as "live". */
+ if (rclass == SGPR_REGS && VECTOR_MODE_P (mode))
+ return CEIL (GET_MODE_SIZE (GET_MODE_INNER (mode)), 4);
+
return CEIL (GET_MODE_SIZE (mode), 4);
}
@@ -3239,6 +3248,10 @@ move_callee_saved_registers (rtx sp, machine_function *offsets,
emit_insn (move_vectors);
emit_insn (move_scalars);
}
+
+ /* This happens when a new register becomes "live" after reload.
+ Check your splitters! */
+ gcc_assert (offset <= offsets->callee_saves);
}
/* Generate prologue. Called from gen_prologue during pro_and_epilogue pass.