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| author | Michael Meissner <meissner@gcc.gnu.org> | 1995-04-18 18:08:17 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 1995-04-18 18:08:17 +0000 |
| commit | 3b7f6cca3532086bcd6675e87bacfcf680a8a8ee (patch) | |
| tree | f4207e14e405f3f841cb96680d80cb7947d1599b | |
| parent | eb0430f02e045c3539a9d4120bc1bbde8925e7ad (diff) | |
| download | gcc-3b7f6cca3532086bcd6675e87bacfcf680a8a8ee.zip gcc-3b7f6cca3532086bcd6675e87bacfcf680a8a8ee.tar.gz gcc-3b7f6cca3532086bcd6675e87bacfcf680a8a8ee.tar.bz2 | |
Do not generate mem->mem SF moves if -msoft-float
From-SVN: r9408
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1b25361..cef070d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3923,7 +3923,10 @@ && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) operands[1] = alter_subreg (operands[1]); - if (TARGET_HARD_FLOAT) + if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM) + operands[1] = force_reg (SFmode, operands[1]); + + else if (TARGET_HARD_FLOAT) { if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) { @@ -3956,7 +3959,7 @@ /* If operands[1] is a register, it may have double-precision data in it, so truncate it to single precision. We need not do this for POWERPC. */ - if (! TARGET_POWERPC && TARGET_HARD_FLOAT && GET_CODE (operands[1]) == REG) + if (! TARGET_POWERPC && GET_CODE (operands[1]) == REG) { rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode); emit_insn (gen_truncdfsf2 (newreg, |