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authorUros Bizjak <ubizjak@gmail.com>2019-07-01 20:41:09 +0200
committerUros Bizjak <uros@gcc.gnu.org>2019-07-01 20:41:09 +0200
commit37d8d439f2ab41a5edad09774f122d58730b26b3 (patch)
treec8c10685d11455fdf0168ce0a8a56b239c516837
parenta3185de66be126c32508f7da8944585d9272d846 (diff)
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i386.md ("isa" attribute): Add sse_noavx.
* config/i386/i386.md ("isa" attribute): Add sse_noavx. ("enabled" attribute): Handle sse_noavx isa attribute. * config/i386/mmx.md (*vec_dupv2sf): Add "isa" attribute. Use TARGET_SSE && SSE_REGNO_P in split condition. (*vec_dupv2sf): Ditto. From-SVN: r272902
-rw-r--r--gcc/ChangeLog8
-rw-r--r--gcc/config/i386/i386.md4
-rw-r--r--gcc/config/i386/mmx.md24
3 files changed, 27 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bd4c8c5..fd2ebf1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-07-01 Uroš Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md ("isa" attribute): Add sse_noavx.
+ ("enabled" attribute): Handle sse_noavx isa attribute.
+ * config/i386/mmx.md (*vec_dupv2sf): Add "isa" attribute.
+ Use TARGET_SSE && SSE_REGNO_P in split condition.
+ (*vec_dupv2sf): Ditto.
+
2019-07-01 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (extenddf<mode>2_fprs): Make this a
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index c362a72..c401deb 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -794,7 +794,7 @@
;; Used to control the "enabled" attribute on a per-instruction basis.
(define_attr "isa" "base,x64,x64_sse2,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
- sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
+ sse_noavx,sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
avx512bw,noavx512bw,avx512dq,noavx512dq,
avx512vl,noavx512vl,x64_avx512dq,x64_avx512bw"
@@ -820,6 +820,8 @@
(symbol_ref "TARGET_64BIT && TARGET_AVX512BW")
(eq_attr "isa" "nox64") (symbol_ref "!TARGET_64BIT")
(eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2")
+ (eq_attr "isa" "sse_noavx")
+ (symbol_ref "TARGET_SSE && !TARGET_AVX")
(eq_attr "isa" "sse2_noavx")
(symbol_ref "TARGET_SSE2 && !TARGET_AVX")
(eq_attr "isa" "sse3") (symbol_ref "TARGET_SSE3")
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 7041334..9ff86ba 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -590,12 +590,16 @@
punpckldq\t%0, %0
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(set (match_dup 0)
(vec_duplicate:V4SF (match_dup 1)))]
- "operands[0] = lowpart_subreg (V4SFmode, operands[0],
- GET_MODE (operands[0]));"
- [(set_attr "mmx_isa" "native,sse_noavx,avx")
+{
+ operands[0] = lowpart_subreg (V4SFmode, operands[0],
+ GET_MODE (operands[0]));
+}
+ [(set_attr "isa" "*,sse_noavx,avx")
+ (set_attr "mmx_isa" "native,*,*")
(set_attr "type" "mmxcvt,ssemov,ssemov")
(set_attr "mode" "DI,TI,TI")])
@@ -1560,12 +1564,16 @@
#
#
#"
- "TARGET_MMX_WITH_SSE && reload_completed"
+ "TARGET_SSE && reload_completed
+ && SSE_REGNO_P (REGNO (operands[0]))"
[(set (match_dup 0)
(vec_duplicate:V4SI (match_dup 1)))]
- "operands[0] = lowpart_subreg (V4SImode, operands[0],
- GET_MODE (operands[0]));"
- [(set_attr "mmx_isa" "native,sse_noavx,avx,avx")
+{
+ operands[0] = lowpart_subreg (V4SImode, operands[0],
+ GET_MODE (operands[0]));
+}
+ [(set_attr "isa" "*,sse_noavx,avx,avx")
+ (set_attr "mmx_isa" "native,*,*,*")
(set_attr "type" "mmxcvt,ssemov,ssemov,ssemov")
(set_attr "mode" "DI,TI,TI,TI")])