arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes

These newly updated tests were rewritten by Andrea. Some of them
needed further manual fixing as follows:

* The #shift immediate value not in the check-function-bodies as expected
* The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In
  this case the test rewritten from the ACLE had the lsr+and pattern,
  but the compiler was able to optimise to ubfx. Hence I've changed the
  test to now match on ubfx.
* Added a separate test to check shift on constants being optimised to
  movs.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/mve_const_shifts.c: New test.

23 files changed, 81 insertions, 128 deletions

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
index 94e3f42..734375d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	srshr	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	srshr	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 int32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
index 65f28cc..a91943c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	srshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	srshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 int64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
index b23c9d9..462531c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	uqshl	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	uqshl	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint32_t
@@ -21,18 +21,6 @@ foo (uint32_t value)
   return uqshl (value, 1);
 }
 
-/*
-**foo1:
-**	...
-**	uqshl	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
-**	...
-*/
-uint32_t
-foo1 ()
-{
-  return uqshl (1, 1);
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
index 6a3d08e..6fa97a5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	uqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	uqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint64_t
@@ -21,18 +21,6 @@ foo (uint64_t value)
   return uqshll (value, 1);
 }
 
-/*
-**foo1:
-**	...
-**	uqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
-**	...
-*/
-uint64_t
-foo1 ()
-{
-  return uqshll (1, 1);
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
index 23afcb8..ff97bf5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	urshr	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	urshr	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint32_t
@@ -24,7 +24,7 @@ foo (uint32_t value)
 /*
 **foo1:
 **	...
-**	urshr	(?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	urshr	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
index 8014371..ff6a69d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
@@ -12,7 +12,7 @@ extern "C" {
 /*
 **foo:
 **	...
-**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint64_t
@@ -24,7 +24,7 @@ foo (uint64_t value)
 /*
 **foo1:
 **	...
-**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?:	@.*|)
+**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
 **	...
 */
 uint64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
index b262bf9..a6a059a 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
index d349cae..9421113 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
index 5166993..3b68bb6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
index 080bd61..8222849 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index 45e6ff0..0d4cb77 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -26,9 +26,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index 54f141b..a0ba682 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -26,9 +26,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
index 06d5bae..47f5f22 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
@@ -22,9 +22,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
index e2111cf..55a961b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
@@ -22,9 +22,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
index 66a5c4c..dcbaef1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
index 9306f15..08f67f6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
index 0b5040f..803246c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
index df211a6..22d2b43 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index 217cfa7..7a33261 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -26,9 +26,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index dad04d0..6090219 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -26,9 +26,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
index cd03364..523fa32 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
@@ -22,9 +22,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
@@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
index 6ca0c75..ff720fd 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
@@ -22,9 +22,7 @@ extern "C" {
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
@@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
 **	...
 **	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
 **	...
-**	lsr	(?:ip|fp|r[0-9]+), #29(?:	@.*|)
-**	...
-**	and	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
 **	...
 */
 uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c
new file mode 100644
index 0000000..b17f9f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c
@@ -0,0 +1,41 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo11:
+**     ...
+**     movs	r0, #2
+**     ...
+*/
+uint32_t
+foo11 ()
+{
+  return uqshl (1, 1);
+}
+
+/*
+**foo12:
+**     ...
+**	movs	r0, #2
+**	movs	r1, #0
+**     ...
+*/
+uint64_t
+foo12 ()
+{
+  return uqshll (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */