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| author | Raphael Moreira Zinsly <rzinsly@ventanamicro.com> | 2023-05-19 21:41:12 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-05-19 21:41:12 -0600 |
| commit | 31cc55f4ff32475f8552205cbf341d4af8bb4fb7 (patch) | |
| tree | c326bd3666ba55d1cf9a8b484eff923b2b815bbe | |
| parent | 9000da00dd70988f30d43806bae33b22ee6b9904 (diff) | |
| download | gcc-31cc55f4ff32475f8552205cbf341d4af8bb4fb7.zip gcc-31cc55f4ff32475f8552205cbf341d4af8bb4fb7.tar.gz gcc-31cc55f4ff32475f8552205cbf341d4af8bb4fb7.tar.bz2 | |
Add bext pattern for ZBS
Changes since v1:
- Removed name clash change.
- Fix new pattern indentation.
-- >8 --
When (a & (1 << bit_no)) is tested inside an IF we can use a bit extract.
gcc/ChangeLog:
* config/riscv/bitmanip.md (branch<X:mode>_bext): New split pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bext-02.c: New test.
| -rw-r--r-- | gcc/config/riscv/bitmanip.md | 23 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbs-bext-02.c | 18 |
2 files changed, 41 insertions, 0 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index c2a29e18..96d31d9 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -767,6 +767,29 @@ operands[9] = GEN_INT (clearbit); }) +;; IF_THEN_ELSE: test for (a & (1 << BIT_NO)) +(define_insn_and_split "*branch<X:mode>_bext" + [(set (pc) + (if_then_else + (match_operator 1 "equality_operator" + [(zero_extract:X (match_operand:X 2 "register_operand" "r") + (const_int 1) + (zero_extend:X + (match_operand:QI 3 "register_operand" "r"))) + (const_int 0)]) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (match_scratch:X 4 "=&r"))] + "TARGET_ZBS" + "#" + "&& reload_completed" + [(set (match_dup 4) (zero_extract:X (match_dup 2) + (const_int 1) + (zero_extend:X (match_dup 3)))) + (set (pc) (if_then_else (match_op_dup 1 [(match_dup 4) (const_int 0)]) + (label_ref (match_dup 0)) + (pc)))]) + ;; ZBKC or ZBC extension (define_insn "riscv_clmul_<mode>" [(set (match_operand:X 0 "register_operand" "=r") diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c b/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c new file mode 100644 index 0000000..3f3b840 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-funroll-loops" } } */ + +int +foo(const long long B, int a) +{ + long long b = 1; + for (int sq = 0; sq < 64; sq++) + if (B & (b << sq)) + a++; + + return a; +} + +/* { dg-final { scan-assembler-times "bext\t" 1 } } */ +/* { dg-final { scan-assembler-not "bset" } } */ +/* { dg-final { scan-assembler-not "and" } } */ |