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| author | Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> | 2023-04-19 14:08:40 +0530 |
|---|---|---|
| committer | Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> | 2023-04-19 14:08:40 +0530 |
| commit | 2c7bf8036dfe2f603f1c135dabf6415d8d28051b (patch) | |
| tree | 7fc8688ecb748e8feb475acf592caa5f7be7de9b | |
| parent | 136330bf637b50a4f10ace017a4316541386b9c0 (diff) | |
| download | gcc-2c7bf8036dfe2f603f1c135dabf6415d8d28051b.zip gcc-2c7bf8036dfe2f603f1c135dabf6415d8d28051b.tar.gz gcc-2c7bf8036dfe2f603f1c135dabf6415d8d28051b.tar.bz2 | |
[aarch64] Use wzr/xzr for assigning 0 to vector element.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_set_zero<mode>):
New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/vec-set-zero.c: New test.
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 14 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vec-set-zero.c | 40 |
2 files changed, 54 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b63c1fe..de2b738 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1083,6 +1083,20 @@ [(set_attr "type" "neon_ins<q>, neon_from_gp<q>, neon_load1_one_lane<q>")] ) +(define_insn "aarch64_simd_vec_set_zero<mode>" + [(set (match_operand:VALL_F16 0 "register_operand" "=w") + (vec_merge:VALL_F16 + (match_operand:VALL_F16 1 "aarch64_simd_imm_zero" "") + (match_operand:VALL_F16 3 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" + { + int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2]))); + operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); + return "ins\\t%0.<Vetype>[%p2], <vwcore>zr"; + } +) + (define_insn "@aarch64_simd_vec_copy_lane<mode>" [(set (match_operand:VALL_F16 0 "register_operand" "=w") (vec_merge:VALL_F16 diff --git a/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c b/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c new file mode 100644 index 0000000..b34b902c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include "arm_neon.h" + +#define FOO(type) \ +type f_##type(type v) \ +{ \ + v[1] = 0; \ + return v; \ +} + +FOO(int8x8_t) +FOO(int16x4_t) +FOO(int32x2_t) + +FOO(int8x16_t) +FOO(int16x8_t) +FOO(int32x4_t) +FOO(int64x2_t) + +FOO(float16x4_t) +FOO(float32x2_t) + +FOO(float16x8_t) +FOO(float32x4_t) +FOO(float64x2_t) + +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.b\[1\], wzr} 2 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.h\[1\], wzr} 4 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.s\[1\], wzr} 4 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.d\[1\], xzr} 2 { target aarch64_little_endian } } } */ + +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.b\[6\], wzr} 1 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.b\[14\], wzr} 1 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.h\[2\], wzr} 2 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.h\[6\], wzr} 2 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.s\[0\], wzr} 2 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.s\[2\], wzr} 2 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times {ins\tv[0-9]+\.d\[0\], xzr} 2 { target aarch64_big_endian } } } */ |