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| author | David S. Miller <davem@davemloft.net> | 2011-10-03 16:41:07 +0000 |
|---|---|---|
| committer | David S. Miller <davem@gcc.gnu.org> | 2011-10-03 09:41:07 -0700 |
| commit | 2b25763bcea8253f124fca96197ce8688f9403ff (patch) | |
| tree | d6d53e4a85d003b05a59f61e13c32985b52b5668 | |
| parent | 1c29961267a210bb8a3284f9ab36ac5076a3fb72 (diff) | |
| download | gcc-2b25763bcea8253f124fca96197ce8688f9403ff.zip gcc-2b25763bcea8253f124fca96197ce8688f9403ff.tar.gz gcc-2b25763bcea8253f124fca96197ce8688f9403ff.tar.bz2 | |
Minor fixups to the sparc bmask/bshuffle patterns.
* config/sparc/sparc.md (bmask<P:mode>_vis): Split into explicit 'di'
and 'si' patterns which describe the GSR changes explicitly in the
RTL using zero_extract.
(bshuffle<V64I:mode>_vis): Put the GSR use inside of the unspec.
From-SVN: r179465
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 27 |
2 files changed, 26 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 028ce8e..9fcee40 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2011-10-03 David S. Miller <davem@davemloft.net> + + * config/sparc/sparc.md (bmask<P:mode>_vis): Split into explicit 'di' + and 'si' patterns which describe the GSR changes explicitly in the + RTL using zero_extract. + (bshuffle<V64I:mode>_vis): Put the GSR use inside of the unspec. + 2011-10-03 Artem Shinkarov <artyom.shinkaroff@gmail.com> * optabs.c (expand_vec_shuffle_expr_p): New function. Checks diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 6990746..c48c979 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -8228,11 +8228,22 @@ "array32\t%r1, %r2, %0" [(set_attr "type" "array")]) -(define_insn "bmask<P:mode>_vis" - [(set (match_operand:P 0 "register_operand" "=r") - (plus:P (match_operand:P 1 "register_operand" "rJ") - (match_operand:P 2 "register_operand" "rJ"))) - (clobber (reg:SI GSR_REG))] +(define_insn "bmaskdi_vis" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (match_operand:DI 1 "register_operand" "rJ") + (match_operand:DI 2 "register_operand" "rJ"))) + (set (zero_extract:DI (reg:DI GSR_REG) (const_int 32) (const_int 32)) + (plus:DI (match_dup 1) (match_dup 2)))] + "TARGET_VIS2" + "bmask\t%r1, %r2, %0" + [(set_attr "type" "array")]) + +(define_insn "bmasksi_vis" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (match_operand:SI 1 "register_operand" "rJ") + (match_operand:SI 2 "register_operand" "rJ"))) + (set (zero_extract:DI (reg:DI GSR_REG) (const_int 32) (const_int 32)) + (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] "TARGET_VIS2" "bmask\t%r1, %r2, %0" [(set_attr "type" "array")]) @@ -8240,9 +8251,9 @@ (define_insn "bshuffle<V64I:mode>_vis" [(set (match_operand:V64I 0 "register_operand" "=e") (unspec:V64I [(match_operand:V64I 1 "register_operand" "e") - (match_operand:V64I 2 "register_operand" "e")] - UNSPEC_BSHUFFLE)) - (use (reg:SI GSR_REG))] + (match_operand:V64I 2 "register_operand" "e") + (use (reg:SI GSR_REG))] + UNSPEC_BSHUFFLE))] "TARGET_VIS2" "bshuffle\t%1, %2, %0" [(set_attr "type" "fga") |