diff options
| author | Jeffrey A Law <law@cygnus.com> | 1999-02-08 21:48:45 +0000 |
|---|---|---|
| committer | Jeff Law <law@gcc.gnu.org> | 1999-02-08 14:48:45 -0700 |
| commit | 29ae5b893490bb4f005b9597946be24be043a080 (patch) | |
| tree | ca5f5d6fcb35de9f14c7d52ed4a47ac472dbafc8 | |
| parent | 20d83a046afd6ae7fdb091cd5ee2e0c27e058b32 (diff) | |
| download | gcc-29ae5b893490bb4f005b9597946be24be043a080.zip gcc-29ae5b893490bb4f005b9597946be24be043a080.tar.gz gcc-29ae5b893490bb4f005b9597946be24be043a080.tar.bz2 | |
rs6000.md: Revert "alternate use of crs if cr0 not available" patches from 01-22-1999...
* rs6000.md: Revert "alternate use of crs if cr0 not available"
patches from 01-22-1999, 01-24-1999, 01-26-1999, and 02-08-1999.
From-SVN: r25102
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 5216 |
2 files changed, 1126 insertions, 4101 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6a6e1ab..9d68691 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Mon Feb 8 22:38:24 1999 Jeffrey A Law (law@cygnus.com) + + * rs6000.md: Revert "alternate use of crs if cr0 not available" + patches from 01-22-1999, 01-24-1999, 01-26-1999, and 02-08-1999. + Mon Feb 8 21:36:44 1999 Richard Henderson <rth@cygnus.com> * output.h (current_function_has_computed_jump): Rename from @@ -707,7 +712,6 @@ Thu Jan 28 09:41:11 1999 Jeffrey A Law (law@cygnus.com) * configure.in (hppa1.0-hp-hpux10*): Use t-pa. * configure: Rebuilt. ->>>>>>> 1.2856 Wed Jan 27 23:39:53 1999 J"orn Rennecke <amylaar@cygnus.co.uk> * rtl.h (insn_first_p): Declare. @@ -744,7 +748,6 @@ Wed Jan 27 23:39:53 1999 J"orn Rennecke <amylaar@cygnus.co.uk> Set derived_regs for givs. * Makefile.in (stmt.o, loop.o, unroll.o): Depend on loop.h . ->>>>>>> 1.2855 Wed Jan 27 19:31:36 1999 J"orn Rennecke <amylaar@cygnus.co.uk> * function.c (purge_addressof_1): Handle case when a register @@ -812,7 +815,6 @@ Tue Jan 26 13:41:38 1999 David Edelsohn <edelsohn@mhpcc.edu> throughout, and invert sense. Put cpp_warning_with_line back in and export it. ->>>>>>> 1.2854 Tue Jan 26 23:21:49 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz> * config/c4x/c4x.h (COUNTER_REGS): New register class. @@ -846,7 +848,6 @@ Tue Jan 26 23:21:49 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz> Move `string' label just after case '"' so that wide strings don't crash the preprocessor. ->>>>>>> 1.2847 Sun Jan 24 20:13:45 1999 David Edelsohn <edelsohn@mhpcc.edu> * rs6000.md (left shift + set cr patterns): Add missing '#' to @@ -945,7 +946,6 @@ Sat Jan 23 22:34:57 1999 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * varasm.c (assemble_string): Likewise. ->>>>>>> 1.2844 Sat Jan 23 01:37:36 1999 Jeffrey A Law (law@cygnus.com) * configure.in (gcc_tooldir): Handle case where exec_prefix has @@ -1003,7 +1003,6 @@ Fri Jan 22 07:43:01 1999 Jeffrey A Law (law@cygnus.com) * Makefile.in (tooldir): Replace with gcc_tooldir. ->>>>>>> 1.2836 Thu Jan 21 23:21:57 1999 Jeffrey A Law (law@cygnus.com) * m68k.md (ashldi_const): Disable for !TARGET_5200. Fix indention. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b73aa35..a8add63 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -435,56 +435,23 @@ [(set_attr "type" "load,*")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:DI 2 "=r,r"))] - "TARGET_POWERPC64" - "@ - rldicl. %2,%1,0,56 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:DI 2 "=r"))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 2) - (zero_extend:DI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "TARGET_POWERPC64" + "rldicl. %2,%1,0,56" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (match_dup 1)))] "TARGET_POWERPC64" - "@ - rldicl. %0,%1,0,56 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (zero_extend:DI (match_dup 1)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (zero_extend:DI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "rldicl. %0,%1,0,56" + [(set_attr "type" "compare")]) (define_insn "extendqidi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -493,56 +460,23 @@ "extsb %0,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 2 "=r,r"))] + (clobber (match_scratch:DI 2 "=r"))] "TARGET_POWERPC64" - "@ - extsb. %2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 2 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 2) - (sign_extend:DI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "extsb. %2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_dup 1)))] "TARGET_POWERPC64" - "@ - extsb. %0,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (sign_extend:DI (match_dup 1)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (sign_extend:DI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "extsb. %0,%1" + [(set_attr "type" "compare")]) (define_expand "zero_extendhidi2" [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -560,56 +494,23 @@ [(set_attr "type" "load,*")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 2 "=r,r"))] + (clobber (match_scratch:DI 2 "=r"))] "TARGET_POWERPC64" - "@ - rldicl. %2,%1,0,48 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 2 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 2) - (zero_extend:DI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "rldicl. %2,%1,0,48" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (match_dup 1)))] "TARGET_POWERPC64" - "@ - rldicl. %0,%1,0,48 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (zero_extend:DI (match_dup 1)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (zero_extend:DI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "rldicl. %0,%1,0,48" + [(set_attr "type" "compare")]) (define_expand "extendhidi2" [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -627,56 +528,23 @@ [(set_attr "type" "load,*")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 2 "=r,r"))] + (clobber (match_scratch:DI 2 "=r"))] "TARGET_POWERPC64" - "@ - extsh. %2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 2 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 2) - (sign_extend:DI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "extsh. %2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_dup 1)))] "TARGET_POWERPC64" - "@ - extsh. %0,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (sign_extend:DI (match_dup 1)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (sign_extend:DI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "extsh. %0,%1" + [(set_attr "type" "compare")]) (define_expand "zero_extendsidi2" [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -694,56 +562,23 @@ [(set_attr "type" "load,*")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 2 "=r,r"))] + (clobber (match_scratch:DI 2 "=r"))] "TARGET_POWERPC64" - "@ - rldicl. %2,%1,0,32 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 2 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 2) - (zero_extend:DI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "rldicl. %2,%1,0,32" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (match_dup 1)))] "TARGET_POWERPC64" - "@ - rldicl. %0,%1,0,32 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (zero_extend:DI (match_dup 1)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (zero_extend:DI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "rldicl. %0,%1,0,32" + [(set_attr "type" "compare")]) (define_expand "extendsidi2" [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -761,56 +596,23 @@ [(set_attr "type" "load,*")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 2 "=r,r"))] + (clobber (match_scratch:DI 2 "=r"))] "TARGET_POWERPC64" - "@ - extsw. %2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 2 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 2) - (sign_extend:DI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "extsw. %2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_dup 1)))] "TARGET_POWERPC64" - "@ - extsw. %0,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (sign_extend:DI (match_dup 1)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (sign_extend:DI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "extsw. %0,%1" + [(set_attr "type" "compare")]) (define_expand "zero_extendqisi2" [(set (match_operand:SI 0 "gpc_reg_operand" "") @@ -828,56 +630,23 @@ [(set_attr "type" "load,*")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 2 "=r,r"))] + (clobber (match_scratch:SI 2 "=r"))] "" - "@ - {andil.|andi.} %2,%1,0xff - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (zero_extend:SI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "{andil.|andi.} %2,%1,0xff" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_dup 1)))] "" - "@ - {andil.|andi.} %0,%1,0xff - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:SI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "{andil.|andi.} %0,%1,0xff" + [(set_attr "type" "compare")]) (define_expand "extendqisi2" [(use (match_operand:SI 0 "gpc_reg_operand" "")) @@ -901,56 +670,23 @@ "extsb %0,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 2 "=r,r"))] + (clobber (match_scratch:SI 2 "=r"))] "TARGET_POWERPC" - "@ - extsb. %2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 2 ""))] - "TARGET_POWERPC && reload_completed" - [(set (match_dup 2) - (sign_extend:SI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "extsb. %2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (sign_extend:SI (match_dup 1)))] "TARGET_POWERPC" - "@ - extsb. %0,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (sign_extend:SI (match_dup 1)))] - "TARGET_POWERPC && reload_completed" - [(set (match_dup 0) - (sign_extend:SI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "extsb. %0,%1" + [(set_attr "type" "compare")]) (define_expand "extendqisi2_power" [(parallel [(set (match_dup 2) @@ -994,92 +730,23 @@ [(set_attr "type" "load,*")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:HI 2 "=r,r"))] + (clobber (match_scratch:HI 2 "=r"))] "" - "@ - {andil.|andi.} %2,%1,0xff - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:HI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (zero_extend:SI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - " -{ - rtx reg; - int offset; - if (GET_CODE (operands[2]) == REG) - { - reg = operands[2]; - offset = 0; - } - else if (GET_CODE (operands[2]) == SUBREG) - { - reg = SUBREG_REG (operands[2]); - offset = SUBREG_WORD (operands[2]); - } - else - abort (); - - operands[3] = gen_rtx_SUBREG (SImode, reg, offset); -}") + "{andil.|andi.} %2,%1,0xff" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:HI 0 "gpc_reg_operand" "=r") (zero_extend:HI (match_dup 1)))] "" - "@ - {andil.|andi.} %0,%1,0xff - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:HI 0 "gpc_reg_operand" "") - (zero_extend:HI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:HI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 3) - (const_int 0)))] - " -{ - rtx reg; - int offset; - if (GET_CODE (operands[0]) == REG) - { - reg = operands[2]; - offset = 0; - } - else if (GET_CODE (operands[2]) == SUBREG) - { - reg = SUBREG_REG (operands[2]); - offset = SUBREG_WORD (operands[2]); - } - else - abort (); - - operands[3] = gen_rtx_SUBREG (SImode, reg, offset); -}") + "{andil.|andi.} %0,%1,0xff" + [(set_attr "type" "compare")]) (define_expand "extendqihi2" [(use (match_operand:HI 0 "gpc_reg_operand" "")) @@ -1103,92 +770,23 @@ "extsb %0,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:HI 2 "=r,r"))] + (clobber (match_scratch:HI 2 "=r"))] "TARGET_POWERPC" - "@ - extsb. %2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:HI 2 ""))] - "TARGET_POWERPC && reload_completed" - [(set (match_dup 2) - (zero_extend:HI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - " -{ - rtx reg; - int offset; - if (GET_CODE (operands[2]) == REG) - { - reg = operands[2]; - offset = 0; - } - else if (GET_CODE (operands[2]) == SUBREG) - { - reg = SUBREG_REG (operands[2]); - offset = SUBREG_WORD (operands[2]); - } - else - abort (); - - operands[3] = gen_rtx_SUBREG (SImode, reg, offset); -}") + "extsb. %2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:HI 0 "gpc_reg_operand" "=r") (sign_extend:HI (match_dup 1)))] "TARGET_POWERPC" - "@ - extsb. %0,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:HI 0 "gpc_reg_operand" "") - (sign_extend:HI (match_dup 1)))] - "TARGET_POWERPC && reload_completed" - [(set (match_dup 0) - (zero_extend:HI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 3) - (const_int 0)))] - " -{ - rtx reg; - int offset; - if (GET_CODE (operands[0]) == REG) - { - reg = operands[0]; - offset = 0; - } - else if (GET_CODE (operands[0]) == SUBREG) - { - reg = SUBREG_REG (operands[0]); - offset = SUBREG_WORD (operands[0]); - } - else - abort (); - - operands[3] = gen_rtx_SUBREG (SImode, reg, offset); -}") + "extsb. %0,%1" + [(set_attr "type" "compare")]) (define_expand "extendqihi2_power" [(parallel [(set (match_dup 2) @@ -1234,56 +832,23 @@ [(set_attr "type" "load,*")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 2 "=r,r"))] + (clobber (match_scratch:SI 2 "=r"))] "" - "@ - {andil.|andi.} %2,%1,0xffff - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (zero_extend:SI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "{andil.|andi.} %2,%1,0xffff" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_dup 1)))] "" - "@ - {andil.|andi.} %0,%1,0xffff - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:SI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "{andil.|andi.} %0,%1,0xffff" + [(set_attr "type" "compare")]) (define_expand "extendhisi2" [(set (match_operand:SI 0 "gpc_reg_operand" "") @@ -1301,44 +866,23 @@ [(set_attr "type" "load,*")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 2 "=r,r"))] + (clobber (match_scratch:SI 2 "=r"))] "" - "@ - {exts.|extsh.} %2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) + "{exts.|extsh.} %2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "=x,?y") - (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (sign_extend:SI (match_dup 1)))] "" - "@ - {exts.|extsh.} %0,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_operand" "") - (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (sign_extend:SI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (sign_extend:SI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - + "{exts.|extsh.} %0,%1" + [(set_attr "type" "compare")]) ;; Fixed-point arithmetic insns. @@ -1382,67 +926,29 @@ [(set_attr "length" "4,4,4,4")]) (define_insn "*addsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") + (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "reg_or_short_operand" "r,I")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" "@ {cax.|add.} %3,%1,%2 - {ai.|addic.} %3,%1,%2 - # - #" - [(set_attr "type" "compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_short_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (plus:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + {ai.|addic.} %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*addsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") + (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "reg_or_short_operand" "r,I")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (match_dup 1) - (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (plus:SI (match_dup 1) (match_dup 2)))] "" "@ {cax.|add.} %0,%1,%2 - {ai.|addic.} %0,%1,%2 - # - #" - [(set_attr "type" "compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_short_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (plus:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + {ai.|addic.} %0,%1,%2" + [(set_attr "type" "compare")]) ;; Split an add that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. Note that the low-order @@ -1474,56 +980,23 @@ "nor %0,%1,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 2 "=r,r"))] + (clobber (match_scratch:SI 2 "=r"))] "" - "@ - nor. %2,%1,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (not:SI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "nor. %2,%1,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (not:SI (match_dup 1)))] - "" - "@ - nor. %0,%1,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r") (not:SI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (not:SI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "" + "nor. %0,%1,%1" + [(set_attr "type" "compare")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1542,121 +1015,46 @@ subfic %0,%2,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "! TARGET_POWERPC" - "@ - {sf.|subfc.} %3,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC && reload_completed" - [(set (match_dup 3) - (minus:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "{sf.|subfc.} %3,%2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "TARGET_POWERPC" - "@ - subf. %3,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "TARGET_POWERPC && reload_completed" - [(set (match_dup 3) - (minus:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "subf. %3,%2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "! TARGET_POWERPC" - "@ - {sf.|subfc.} %0,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (minus:SI (match_dup 1) - (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (minus:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "{sf.|subfc.} %0,%2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (minus:SI (match_dup 1) - (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (minus:SI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC" "subf. %0,%2,%1" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_short_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (minus:SI (match_dup 1) - (match_dup 2)))] - "TARGET_POWERPC && reload_completed" - [(set (match_dup 0) - (minus:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + [(set_attr "type" "compare")]) (define_expand "subsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") @@ -1774,86 +1172,34 @@ "doz%I2 %0,%1,%2") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) + (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "TARGET_POWER" - "@ - doz%I2. %3,%1,%2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "=x,?y") - (compare:CC - (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) - (const_int 0) - (minus:SI (match_dup 2) (match_dup 1))) - (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] - "TARGET_POWER && reload_completed" - [(set (match_dup 3) - (if_then_else:SI (gt (match_dup 1) - (match_dup 2)) - (const_int 0) - (minus:SI (match_dup 2) - (match_dup 1)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "doz%I2. %3,%1,%2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) + (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (if_then_else:SI (gt (match_dup 1) (match_dup 2)) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))))] "TARGET_POWER" - "@ - doz%I2. %0,%1,%2 - #" + "doz%I2. %0,%1,%2" [(set_attr "type" "delayed_compare")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "=x,?y") - (compare:CC - (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) - (const_int 0) - (minus:SI (match_dup 2) (match_dup 1))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (if_then_else:SI (gt (match_dup 1) - (match_dup 2)) - (const_int 0) - (minus:SI (match_dup 2) - (match_dup 1))))] - "TARGET_POWER && reload_completed" - [(set (match_dup 0) - (if_then_else:SI (gt (match_dup 1) - (match_dup 2)) - (const_int 0) - (minus:SI (match_dup 2) - (match_dup 1)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - ;; We don't need abs with condition code because such comparisons should ;; never be done. (define_expand "abssi2" @@ -1934,56 +1280,23 @@ "neg %0,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 2 "=r,r"))] + (clobber (match_scratch:SI 2 "=r"))] "" - "@ - neg. %2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (neg:SI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "neg. %2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (neg:SI (match_dup 1)))] - "" - "@ - neg. %0,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r") (neg:SI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (neg:SI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "" + "neg. %0,%1" + [(set_attr "type" "compare")]) (define_insn "ffssi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") @@ -2028,129 +1341,48 @@ [(set_attr "type" "imul")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r")) - (clobber (match_scratch:SI 4 "=q,q"))] + (clobber (match_scratch:SI 3 "=r")) + (clobber (match_scratch:SI 4 "=q"))] "TARGET_POWER" - "@ - {muls.|mullw.} %3,%1,%2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 "")) - (clobber (match_scratch:SI 4 ""))] - "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 3) - (mult:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "{muls.|mullw.} %3,%1,%2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "! TARGET_POWER" - "@ - {muls.|mullw.} %3,%1,%2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (mult:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "{muls.|mullw.} %3,%1,%2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (mult:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:SI 4 "=q,q"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (mult:SI (match_dup 1) (match_dup 2))) + (clobber (match_scratch:SI 4 "=q"))] "TARGET_POWER" - "@ - {muls.|mullw.} %0,%1,%2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (mult:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:SI 4 ""))] - "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) - (mult:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "{muls.|mullw.} %0,%1,%2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (mult:SI (match_dup 1) (match_dup 2)))] "! TARGET_POWER" - "@ - {muls.|mullw.} %0,%1,%2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (mult:SI (match_dup 1) - (match_dup 2)))] - "!TARGET_POWER && reload_completed" - [(set (match_dup 0) - (mult:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "{muls.|mullw.} %0,%1,%2" + [(set_attr "type" "delayed_compare")]) ;; Operand 1 is divided by operand 2; quotient goes to operand ;; 0 and remainder to operand 3. @@ -2309,64 +1541,27 @@ [(set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "N,N")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "N")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "exact_log2 (INTVAL (operands[2])) >= 0" - "@ - {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 - #" + "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed && exact_log2 (INTVAL (operands[2])) >= 0" - [(set (match_dup 3) - (div:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + (set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "N,N")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "N")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (div:SI (match_dup 1) - (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (div:SI (match_dup 1) (match_dup 2)))] "exact_log2 (INTVAL (operands[2])) >= 0" - "@ - {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 - #" + "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_short_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (div:SI (match_dup 1) - (match_dup 2)))] - "reload_completed" - [(set (match_dup 3) - (div:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -2539,131 +1734,47 @@ [(set_attr "type" "idiv")]) ;; Logical instructions -(define_expand "andsi3" - [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:SI 2 "and_operand" "?r,L,K,J"))) - (clobber (match_scratch:CC 3 "=X,X,x,x"))])] - "" - "") - -;; If cr0 isn't available, and we want to do an andi, load the register into -;; the destination first. - -(define_insn "andsi3_internal1" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,&??r,&??r") - (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r") - (match_operand:SI 2 "and_operand" "?r,L,K,J,K,J"))) - (clobber (match_operand:CC 3 "scratch_operand" "=X,X,x,x,X,X"))] +(define_insn "andsi3" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") + (match_operand:SI 2 "and_operand" "?r,L,K,J"))) + (clobber (match_scratch:CC 3 "=X,X,x,x"))] "" "@ and %0,%1,%2 {rlinm|rlwinm} %0,%1,0,%m2,%M2 {andil.|andi.} %0,%1,%b2 - {andiu.|andis.} %0,%1,%u2 - # - #" - [(set_attr "length" "4,4,4,4,8,8")]) - -(define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" ""))) - (clobber (scratch:CC))] - "reload_completed && !mask_constant (INTVAL (operands[2]))" - [(set (match_dup 0) - (match_dup 2)) - (parallel [(set (match_dup 0) - (and:SI (match_dup 0) - (match_dup 1))) - (clobber (scratch:CC))])] - "") - -;; Note to set cr's other than cr0 we do the and immediate and then -;; the test again -- this avoids a mcrf which on the higher end -;; machines causes an execution serialization + {andiu.|andis.} %0,%1,%u2" + [(set_attr "length" "4,4,4,4")]) (define_insn "*andsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L,K,L")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") + (match_operand:SI 2 "and_operand" "r,K,J,L")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r,&r,&r")) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))] + (clobber (match_scratch:SI 3 "=r,r,r,r"))] "" "@ and. %3,%1,%2 {andil.|andi.} %3,%1,%b2 {andiu.|andis.} %3,%1,%u2 - {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 - # - # - # - # - # - #" - [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare") - (set_attr "length" "4,4,4,4,8,8,8,8,12,12")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "and_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 "")) - (clobber (match_scratch:CC 4 ""))] - "reload_completed" - [(parallel [(set (match_dup 3) - (and:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + {rlinm.|rlwinm.} %3,%1,0,%m2,%M2" + [(set_attr "type" "compare,compare,compare,delayed_compare")]) (define_insn "*andsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L,K,J")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") + (match_operand:SI 2 "and_operand" "r,K,J,L")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,&r,&r") - (and:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (and:SI (match_dup 1) (match_dup 2)))] "" "@ and. %0,%1,%2 {andil.|andi.} %0,%1,%b2 {andiu.|andis.} %0,%1,%u2 - {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 - # - # - # - # - # - #" - [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare") - (set_attr "length" "4,4,4,4,8,8,8,8,12,12")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "and_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:CC 4 ""))] - "reload_completed" - [(parallel [(set (match_dup 0) - (and:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + {rlinm.|rlwinm.} %0,%1,0,%m2,%M2" + [(set_attr "type" "compare,compare,compare,delayed_compare")]) (define_expand "iorsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") @@ -2699,63 +1810,26 @@ [(set_attr "length" "4,4,4")]) (define_insn "*iorsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "" - "@ - or. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (ior:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "or. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*iorsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ior:SI (match_dup 1) - (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (match_dup 1) (match_dup 2)))] "" - "@ - or. %0,%1,%2 - #" + "or. %0,%1,%2" [(set_attr "type" "compare")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ior:SI (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (ior:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - ;; Split an IOR that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. @@ -2806,63 +1880,25 @@ [(set_attr "length" "4,4,4")]) (define_insn "*xorsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "" - "@ - xor. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (xor:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "xor. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*xorsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (xor:SI (match_dup 1) - (match_dup 2)))] - "" - "@ - xor. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (xor:SI (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (xor:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "" + "xor. %0,%1,%2" + [(set_attr "type" "compare")]) ;; Split an XOR that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. @@ -2888,63 +1924,25 @@ "eqv %0,%1,%2") (define_insn "*eqvsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "" - "@ - eqv. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (not:SI (xor:SI (match_dup 1) - (match_dup 2)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "eqv. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*eqvsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (not:SI (xor:SI (match_dup 1) (match_dup 2))))] "" - "@ - eqv. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_short_operand" ""))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (not:SI (xor:SI (match_dup 1) - (match_dup 2))))] - "reload_completed" - [(set (match_dup 0) - (not:SI (xor:SI (match_dup 1) - (match_dup 2)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "eqv. %0,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*andcsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -2954,64 +1952,25 @@ "andc %0,%2,%1") (define_insn "*andcsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "" - "@ - andc. %3,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (and:SI (not:SI (match_dup 1)) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "andc. %3,%2,%1" + [(set_attr "type" "compare")]) (define_insn "*andcsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (not:SI (match_dup 1)) - (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (not:SI (match_dup 1)) (match_dup 2)))] "" - "@ - andc. %0,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (not:SI (match_dup 1)) - (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (and:SI (not:SI (match_dup 1)) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "andc. %0,%2,%1" + [(set_attr "type" "compare")]) (define_insn "*iorcsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -3021,196 +1980,81 @@ "orc %0,%2,%1") (define_insn "*iorcsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "" - "@ - orc. %3,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (ior:SI (not:SI (match_dup 1)) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "orc. %3,%2,%1" + [(set_attr "type" "compare")]) (define_insn "*iorcsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] "" - "@ - orc. %0,%2,%1 - #" + "orc. %0,%2,%1" [(set_attr "type" "compare")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ior:SI (not:SI (match_dup 1)) - (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (ior:SI (not:SI (match_dup 1)) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "*nandsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "nand %0,%1,%2") (define_insn "*nandsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "" - "@ - nand. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (ior:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "nand. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*nandsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ior:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2))))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] "" - "@ - nand. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ior:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2))))] - "reload_completed" - [(set (match_dup 0) - (ior:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "nand. %0,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*norsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "nor %0,%1,%2") (define_insn "*norsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "" - "@ - nor. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (and:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "nor. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*norsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2))))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] "" - "@ - nor. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2))))] - "reload_completed" - [(set (match_dup 0) - (and:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "nor. %0,%1,%2" + [(set_attr "type" "compare")]) ;; maskir insn. We need four forms because things might be in arbitrary ;; orders. Don't define forms that only set CR fields because these @@ -3253,166 +2097,64 @@ "maskir %0,%3,%2") (define_insn "*maskir_internal5" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (match_operand:SI 1 "gpc_reg_operand" "0,0")) + (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) + (match_operand:SI 1 "gpc_reg_operand" "0")) (and:SI (match_dup 2) - (match_operand:SI 3 "gpc_reg_operand" "r,r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) (and:SI (match_dup 2) (match_dup 3))))] "TARGET_POWER" - "@ - maskir. %0,%3,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC - (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) - (match_operand:SI 1 "gpc_reg_operand" "")) - (and:SI (match_dup 2) - (match_operand:SI 3 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) - (and:SI (match_dup 2) (match_dup 3))))] - "TARGET_POWER && reload_completed" - [(set (match_dup 0) - (ior:SI (and:SI (not:SI (match_dup 2)) - (match_dup 1)) - (and:SI (match_dup 2) - (match_dup 3)))) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - + "maskir. %0,%3,%2" + [(set_attr "type" "compare")]) (define_insn "*maskir_internal6" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (match_operand:SI 1 "gpc_reg_operand" "0,0")) - (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") + (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) + (match_operand:SI 1 "gpc_reg_operand" "0")) + (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") (match_dup 2))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) (and:SI (match_dup 3) (match_dup 2))))] "TARGET_POWER" - "@ - maskir. %0,%3,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC - (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) - (match_operand:SI 1 "gpc_reg_operand" "")) - (and:SI (match_operand:SI 3 "gpc_reg_operand" "") - (match_dup 2))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) - (and:SI (match_dup 3) (match_dup 2))))] - "TARGET_POWER && reload_completed" - [(set (match_dup 0) - (ior:SI (and:SI (not:SI (match_dup 2)) - (match_dup 1)) - (and:SI (match_dup 3) - (match_dup 2)))) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "maskir. %0,%3,%2" + [(set_attr "type" "compare")]) (define_insn "*maskir_internal7" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC - (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") - (match_operand:SI 3 "gpc_reg_operand" "r,r")) - (and:SI (not:SI (match_dup 2)) - (match_operand:SI 1 "gpc_reg_operand" "0,0"))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ior:SI (and:SI (match_dup 2) (match_dup 3)) - (and:SI (not:SI (match_dup 2)) (match_dup 1))))] - "TARGET_POWER" - "@ - maskir. %0,%3,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") - (match_operand:SI 3 "gpc_reg_operand" "")) + (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand:SI 3 "gpc_reg_operand" "r")) (and:SI (not:SI (match_dup 2)) - (match_operand:SI 1 "gpc_reg_operand" ""))) + (match_operand:SI 1 "gpc_reg_operand" "0"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_dup 2) (match_dup 3)) (and:SI (not:SI (match_dup 2)) (match_dup 1))))] "TARGET_POWER" - [(set (match_dup 0) - (ior:SI (and:SI (match_dup 2) - (match_dup 3)) - (and:SI (not:SI (match_dup 2)) - (match_dup 1)))) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "maskir. %0,%3,%2" + [(set_attr "type" "compare")]) (define_insn "*maskir_internal8" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (and:SI (not:SI (match_dup 2)) - (match_operand:SI 1 "gpc_reg_operand" "0,0"))) + (match_operand:SI 1 "gpc_reg_operand" "0"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_dup 3) (match_dup 2)) (and:SI (not:SI (match_dup 2)) (match_dup 1))))] "TARGET_POWER" - "@ - maskir. %0,%3,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC - (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (and:SI (not:SI (match_dup 2)) - (match_operand:SI 1 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ior:SI (and:SI (match_dup 3) (match_dup 2)) - (and:SI (not:SI (match_dup 2)) (match_dup 1))))] - "TARGET_POWER && reload_completed" - [(set (match_dup 0) - (ior:SI (and:SI (match_dup 3) - (match_dup 2)) - (and:SI (not:SI (match_dup 2)) - (match_dup 1)))) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - + "maskir. %0,%3,%2" + [(set_attr "type" "compare")]) ;; Rotate and shift insns, in all their variants. These support shifts, ;; field inserts and extracts, and various combinations thereof. @@ -3573,22 +2315,18 @@ }") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i") - (match_operand:SI 3 "const_int_operand" "i,i")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i") + (match_operand:SI 3 "const_int_operand" "i")) (const_int 0))) - (clobber (match_scratch:SI 4 "=r,r"))] + (clobber (match_scratch:SI 4 "=r"))] "" "* { int start = INTVAL (operands[3]) & 31; int size = INTVAL (operands[2]) & 31; - /* Split insn if not setting cr0. */ - if (cc_reg_not_cr0_operand (operands[0], CCmode)) - return \"#\"; - /* If the bitfield being tested fits in the upper or lower half of a word, it is possible to use andiu. or andil. to test it. This is useful because the condition register set-use delay is smaller for @@ -3611,33 +2349,15 @@ operands[3] = GEN_INT (start + size); return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; }" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "") - (match_operand:SI 3 "const_int_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 4 ""))] - "reload_completed" - [(set (match_dup 4) - (zero_extract:SI (match_dup 1) - (match_dup 2) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i") - (match_operand:SI 3 "const_int_operand" "i,i")) + [(set (match_operand:CC 4 "cc_reg_operand" "=x") + (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i") + (match_operand:SI 3 "const_int_operand" "i")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] "" "* @@ -3645,10 +2365,6 @@ int start = INTVAL (operands[3]) & 31; int size = INTVAL (operands[2]) & 31; - /* Split insn if not setting cr0. */ - if (cc_reg_not_cr0_operand (operands[0], CCmode)) - return \"#\"; - if (start >= 16 && start + size == 32) { operands[3] = GEN_INT ((1 << (32 - start)) - 1); @@ -3663,26 +2379,6 @@ }" [(set_attr "type" "delayed_compare")]) -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "") - (match_operand:SI 3 "const_int_operand" "")) - (const_int 0))) - (set (match_dup 0) - (zero_extract:SI (match_dup 1) - (match_dup 2) - (match_dup 3)))] - "reload_completed" - [(set (match_dup 0) - (zero_extract:SI (match_dup 1) - (match_dup 2) - (match_dup 3))) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") @@ -3703,22 +2399,18 @@ }") (define_insn "" - [(set (match_operand:CC 0 "gpc_reg_operand" "=x,?y") - (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "const_int_operand" "i,i") - (match_operand:DI 3 "const_int_operand" "i,i")) + [(set (match_operand:CC 0 "gpc_reg_operand" "=x") + (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "const_int_operand" "i") + (match_operand:DI 3 "const_int_operand" "i")) (const_int 0))) - (clobber (match_scratch:DI 4 "=r,r"))] + (clobber (match_scratch:DI 4 "=r"))] "TARGET_POWERPC64" "* { int start = INTVAL (operands[3]) & 63; int size = INTVAL (operands[2]) & 63; - /* Split insn if not setting cr0. */ - if (cc_reg_not_cr0_operand (operands[0], CCmode)) - return \"#\"; - if (start + size >= 64) operands[3] = const0_rtx; else @@ -3727,30 +2419,13 @@ return \"rldicl. %4,%1,%3,%2\"; }") -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "const_int_operand" "") - (match_operand:DI 3 "const_int_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 4 ""))] - "reload_completed" - [(set (match_dup 4) - (zero_extract:DI (match_dup 1) - (match_dup 2) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") - (define_insn "" - [(set (match_operand:CC 4 "gpc_reg_operand" "=x,?y") - (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "const_int_operand" "i,i") - (match_operand:DI 3 "const_int_operand" "i,i")) + [(set (match_operand:CC 4 "gpc_reg_operand" "=x") + (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "const_int_operand" "i") + (match_operand:DI 3 "const_int_operand" "i")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] "TARGET_POWERPC64" "* @@ -3758,10 +2433,6 @@ int start = INTVAL (operands[3]) & 63; int size = INTVAL (operands[2]) & 63; - /* Split insn if not setting cr0. */ - if (cc_reg_not_cr0_operand (operands[0], CCmode)) - return \"#\"; - if (start + size >= 64) operands[3] = const0_rtx; else @@ -3770,26 +2441,6 @@ return \"rldicl. %0,%1,%3,%2\"; }") -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "const_int_operand" "") - (match_operand:DI 3 "const_int_operand" "")) - (const_int 0))) - (set (match_dup 0) - (zero_extract:DI (match_dup 1) - (match_dup 2) - (match_dup 3)))] - "reload_completed" - [(set (match_dup 0) - (zero_extract:DI (match_dup 1) - (match_dup 2) - (match_dup 3))) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "rotlsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") @@ -3798,63 +2449,25 @@ "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") (define_insn "*rotlsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "" - "@ - {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (rotate:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotlsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (rotate:SI (match_dup 1) (match_dup 2)))] "" - "@ - {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (rotate:SI (match_dup 1) - (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (rotate:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotlsi3_internal4" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -3865,75 +2478,29 @@ "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") (define_insn "*rotlsi3_internal5" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) - (match_operand:SI 3 "mask_operand" "L,L")) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) + (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (clobber (match_scratch:SI 4 "=r,r"))] + (clobber (match_scratch:SI 4 "=r"))] "" - "@ - {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 4 ""))] - "reload_completed" - [(set (match_dup 4) - (and:SI (rotate:SI (match_dup 1) - (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") + "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotlsi3_internal6" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) - (match_operand:SI 3 "mask_operand" "L,L")) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) + (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "" - "@ - {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI - (rotate:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))] - "reload_completed" - [(set (match_dup 0) - (and:SI (rotate:SI (match_dup 1) - (match_dup 2)) - (match_dup 3))) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotlsi3_internal7" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -3945,75 +2512,30 @@ "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") (define_insn "*rotlsi3_internal8" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "" - "@ - {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) + "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff" + [(set_attr "type" "delayed_compare")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:SI - (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (zero_extend:SI - (subreg:QI - (rotate:SI (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - (define_insn "*rotlsi3_internal9" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "" - "@ - {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) + "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff" + [(set_attr "type" "delayed_compare")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "=x,?y") - (compare:CC (zero_extend:SI - (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:SI - (subreg:QI - (rotate:SI (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "*rotlsi3_internal10" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI @@ -4024,74 +2546,29 @@ "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") (define_insn "*rotlsi3_internal11" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "" - "@ - {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:SI - (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (zero_extend:SI - (subreg:HI - (rotate:SI (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotlsi3_internal12" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "" - "@ - {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "=x,?y") - (compare:CC (zero_extend:SI - (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:SI - (subreg:HI - (rotate:SI (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff" + [(set_attr "type" "delayed_compare")]) ;; Note that we use "sle." instead of "sl." so that we can set ;; SHIFT_COUNT_TRUNCATED. @@ -4130,129 +2607,53 @@ [(set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") + (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r")) - (clobber (match_scratch:SI 4 "=q,X,q,X"))] + (clobber (match_scratch:SI 3 "=r,r")) + (clobber (match_scratch:SI 4 "=q,X"))] "TARGET_POWER" "@ sle. %3,%1,%2 - {sli.|slwi.} %3,%1,%h2 - # - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 "")) - (clobber (match_scratch:SI 4 ""))] - "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 3) - (ashift:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + {sli.|slwi.} %3,%1,%h2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "! TARGET_POWER" - "@ - {sl|slw}%I2. %3,%1,%h2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWER && reload_completed" - [(set (match_dup 3) - (ashift:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "{sl|slw}%I2. %3,%1,%h2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") + (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashift:SI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:SI 4 "=q,X,q,X"))] + (clobber (match_scratch:SI 4 "=q,X"))] "TARGET_POWER" "@ sle. %0,%1,%2 - {sli.|slwi.} %0,%1,%h2 - # - #" + {sli.|slwi.} %0,%1,%h2" [(set_attr "type" "delayed_compare")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ashift:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:SI 4 ""))] - "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) - (ashift:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ashift:SI (match_dup 1) (match_dup 2)))] "! TARGET_POWER" "{sl|slw}%I2. %0,%1,%h2" [(set_attr "type" "delayed_compare")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ashift:SI (match_dup 1) - (match_dup 2)))] - "! TARGET_POWER && reload_completed" - [(set (match_dup 0) - (ashift:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") @@ -4262,73 +2663,30 @@ "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:SI 3 "mask_operand" "L,L")) + (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) + (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (clobber (match_scratch:SI 4 "=r,r"))] + (clobber (match_scratch:SI 4 "=r"))] "includes_lshift_p (operands[2], operands[3])" - "@ - {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 - #" + "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3" [(set_attr "type" "delayed_compare")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC - (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 4 ""))] - "reload_completed && includes_lshift_p (operands[2], operands[3])" - [(set (match_dup 4) - (and:SI (ashift:SI (match_dup 1) - (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") - (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:SI 3 "mask_operand" "L,L")) + (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) + (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "includes_lshift_p (operands[2], operands[3])" - "@ - {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 - #" + "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3" [(set_attr "type" "delayed_compare")]) -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC - (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (ashift:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))] - "reload_completed && includes_lshift_p (operands[2], operands[3])" - [(set (match_dup 4) - (and:SI (ashift:SI (match_dup 1) - (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") - ;; The AIX assembler mis-handles "sri x,x,0", so write that case as ;; "sli x,x,0". (define_expand "lshrsi3" @@ -4366,140 +2724,58 @@ {sr|srw}%I2 %0,%1,%h2") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,y,?y") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x") + (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) - (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] + (clobber (match_scratch:SI 3 "=r,X,r")) + (clobber (match_scratch:SI 4 "=q,X,X"))] "TARGET_POWER" "@ - sre. %3,%1,%2 - mr. %1,%1 - {s%A2i.|s%A2wi.} %3,%1,%h2 - # - cmpli %0,%1,0 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,4,4,8,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 "")) - (clobber (match_scratch:SI 4 ""))] - "TARGET_POWER && reload_completed - && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)" - [(parallel [(set (match_dup 3) - (lshiftrt:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + sre. %3,%1,%2 + mr. %1,%1 + {s%A2i.|s%A2wi.} %3,%1,%h2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,y,?y") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") + (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "O,ri")) (const_int 0))) - (clobber (match_scratch:SI 3 "=X,r,X,r"))] + (clobber (match_scratch:SI 3 "=X,r"))] "! TARGET_POWER" "@ mr. %1,%1 - {sr|srw}%I2. %3,%1,%h2 - cmpli %0,%1,0 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,4,4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWER && reload_completed - && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)" - [(set (match_dup 3) - (lshiftrt:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + {sr|srw}%I2. %3,%1,%h2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,rOi")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x") + (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (lshiftrt:SI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:SI 4 "=q,X,X,q"))] + (clobber (match_scratch:SI 4 "=q,X,X"))] "TARGET_POWER" "@ - sre. %0,%1,%2 - mr. %0,%1 - {s%A2i.|s%A2wi.} %0,%1,%h2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,4,4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (lshiftrt:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:SI 4 ""))] - "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 3) - (lshiftrt:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + sre. %0,%1,%2 + mr. %0,%1 + {s%A2i.|s%A2wi.} %0,%1,%h2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") + (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "O,ri")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (lshiftrt:SI (match_dup 1) (match_dup 2)))] "! TARGET_POWER" "@ mr. %0,%1 - {sr|srw}%I2. %0,%1,%h2 - # - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (lshiftrt:SI (match_dup 1) - (match_dup 2)))] - "! TARGET_POWER && reload_completed" - [(set (match_dup 0) - (lshiftrt:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + {sr|srw}%I2. %0,%1,%h2" + [(set_attr "type" "delayed_compare")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -4510,74 +2786,29 @@ "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:SI 3 "mask_operand" "L,L")) + (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) + (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (clobber (match_scratch:SI 4 "=r,r"))] + (clobber (match_scratch:SI 4 "=r"))] "includes_rshift_p (operands[2], operands[3])" - "@ - {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC - (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 4 ""))] - "reload_completed && includes_rshift_p (operands[2], operands[3])" - [(set (match_dup 4) - (and:SI (lshiftrt:SI (match_dup 1) - (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") + "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:SI 3 "mask_operand" "L,L")) + (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) + (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "includes_rshift_p (operands[2], operands[3])" - "@ - {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC - (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (lshiftrt:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))] - "reload_completed && includes_rshift_p (operands[2], operands[3])" - [(set (match_dup 4) - (and:SI (lshiftrt:SI (match_dup 1) - (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") + "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3" + [(set_attr "type" "delayed_compare")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -4589,81 +2820,31 @@ "{rlinm|rlwinm} %0,%1,%s2,0xff") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:QI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i")) 0)) + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "includes_rshift_p (operands[2], GEN_INT (255))" - "@ - {rlinm.|rlwinm.} %3,%1,%s2,0xff - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC - (zero_extend:SI - (subreg:QI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) 0)) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))" - [(set (match_dup 3) - (zero_extend:SI - (subreg:QI - (lshiftrt:SI (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "{rlinm.|rlwinm.} %3,%1,%s2,0xff" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:QI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i")) 0)) + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] "includes_rshift_p (operands[2], GEN_INT (255))" - "@ - {rlinm.|rlwinm.} %0,%1,%s2,0xff - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC - (zero_extend:SI - (subreg:QI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) 0)) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI - (subreg:QI - (lshiftrt:SI (match_dup 1) - (match_dup 2)) 0)))] - "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))" - [(set (match_dup 0) - (zero_extend:SI - (subreg:QI - (lshiftrt:SI (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "{rlinm.|rlwinm.} %0,%1,%s2,0xff" + [(set_attr "type" "delayed_compare")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -4674,80 +2855,33 @@ "includes_rshift_p (operands[2], GEN_INT (65535))" "{rlinm|rlwinm} %0,%1,%s2,0xffff") -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC - (zero_extend:SI - (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) 0)) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))" - [(set (match_dup 3) - (zero_extend:SI - (subreg:HI - (lshiftrt:SI (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i")) 0)) + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "includes_rshift_p (operands[2], GEN_INT (65535))" - "@ - {rlinm.|rlwinm.} %3,%1,%s2,0xffff - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) + "{rlinm.|rlwinm.} %3,%1,%s2,0xffff" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i")) 0)) + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] "includes_rshift_p (operands[2], GEN_INT (65535))" "{rlinm.|rlwinm.} %0,%1,%s2,0xffff" [(set_attr "type" "delayed_compare")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC - (zero_extend:SI - (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) 0)) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI - (subreg:HI - (lshiftrt:SI (match_dup 1) - (match_dup 2)) 0)))] - "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))" - [(set (match_dup 0) - (zero_extend:SI - (subreg:HI - (lshiftrt:SI (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 1) @@ -4808,132 +2942,52 @@ "{sra|sraw}%I2 %0,%1,%h2") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") + (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r")) - (clobber (match_scratch:SI 4 "=q,X,q,X"))] + (clobber (match_scratch:SI 3 "=r,r")) + (clobber (match_scratch:SI 4 "=q,X"))] "TARGET_POWER" "@ srea. %3,%1,%2 - {srai.|srawi.} %3,%1,%h2 - # - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 "")) - (clobber (match_scratch:SI 4 ""))] - "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 3) - (ashiftrt:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + {srai.|srawi.} %3,%1,%h2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "! TARGET_POWER" - "@ - {sra|sraw}%I2. %3,%1,%h2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (ashiftrt:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "{sra|sraw}%I2. %3,%1,%h2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") + (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashiftrt:SI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:SI 4 "=q,X,q,X"))] + (clobber (match_scratch:SI 4 "=q,X"))] "TARGET_POWER" "@ srea. %0,%1,%2 - {srai.|srawi.} %0,%1,%h2 - # - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ashiftrt:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:SI 4 ""))] - "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) - (ashiftrt:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + {srai.|srawi.} %0,%1,%h2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ashiftrt:SI (match_dup 1) (match_dup 2)))] "! TARGET_POWER" - "@ - {sra|sraw}%I2. %0,%1,%h2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ashiftrt:SI (match_dup 1) - (match_dup 2)))] - "! TARGET_POWER && reload_completed" - [(set (match_dup 0) - (ashiftrt:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "{sra|sraw}%I2. %0,%1,%h2" + [(set_attr "type" "delayed_compare")]) ;; Floating-point insns, excluding normal data motion. ;; @@ -6340,67 +4394,29 @@ addis %0,%1,%v2") (define_insn "*adddi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") + (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") + (match_operand:DI 2 "reg_or_short_operand" "r,I")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_POWERPC64" "@ add. %3,%1,%2 - addic. %3,%1,%2 - # - #" - [(set_attr "type" "compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_short_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (plus:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + addic. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*adddi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") + (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") + (match_operand:DI 2 "reg_or_short_operand" "r,I")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (plus:DI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64" "@ add. %0,%1,%2 - addic. %0,%1,%2 - # - #" - [(set_attr "type" "compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_short_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (plus:DI (match_dup 1) - (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (plus:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + addic. %0,%1,%2" + [(set_attr "type" "compare")]) ;; Split an add that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. Note that the low-order @@ -6432,52 +4448,24 @@ "nor %0,%1,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 2 "=r,r"))] + (clobber (match_scratch:DI 2 "=r"))] "TARGET_POWERPC64" "nor. %2,%1,%1" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (not:DI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (not:DI (match_dup 1)))] "TARGET_POWERPC64" "nor. %0,%1,%1" [(set_attr "type" "compare")]) -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (not:DI (match_dup 1)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (not:DI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") @@ -6488,59 +4476,26 @@ subfic %0,%2,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" "subf. %3,%2,%1" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (minus:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (minus:DI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64" "subf. %0,%2,%1" [(set_attr "type" "compare")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (minus:DI (match_dup 1) - (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (minus:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_expand "subdi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") @@ -6605,56 +4560,23 @@ "neg %0,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 2 "=r,r"))] + (clobber (match_scratch:DI 2 "=r"))] "TARGET_POWERPC64" - "@ - neg. %2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 2 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 2) - (neg:DI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") + "neg. %2,%1" + [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (neg:DI (match_dup 1)))] "TARGET_POWERPC64" - "@ - neg. %0,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (neg:DI (match_dup 1)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (neg:DI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "neg. %0,%1" + [(set_attr "type" "compare")]) (define_insn "ffsdi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") @@ -6741,63 +4663,27 @@ [(set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "const_int_operand" "N,N")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "const_int_operand" "N")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" - "@ - sradi %3,%1,%p2\;addze. %3,%3 - #" + "sradi %3,%1,%p2\;addze. %3,%3" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "const_int_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed && exact_log2 (INTVAL (operands[2])) >= 0" - [(set (match_dup 3) - (div:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + (set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "const_int_operand" "N,N")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "const_int_operand" "N")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (div:DI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" - "@ - sradi %0,%1,%p2\;addze. %0,%0 - #" + "sradi %0,%1,%p2\;addze. %0,%0" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "const_int_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (div:DI (match_dup 1) - (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed && exact_log2 (INTVAL (operands[2])) >= 0" - [(set (match_dup 0) - (div:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -6823,63 +4709,25 @@ "rld%I2cl %0,%1,%H2,0") (define_insn "*rotldi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - rld%I2cl. %3,%1,%H2,0 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (rotate:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "rld%I2cl. %3,%1,%H2,0" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotldi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (rotate:DI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64" - "@ - rld%I2cl. %0,%1,%H2,0 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (rotate:DI (match_dup 1) - (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (rotate:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "rld%I2cl. %0,%1,%H2,0" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotldi3_internal4" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -6890,77 +4738,29 @@ "rld%I2c%B3 %0,%1,%H2,%S3") (define_insn "*rotldi3_internal5" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (and:DI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) - (match_operand:DI 3 "mask64_operand" "S,S")) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "ri")) + (match_operand:DI 3 "mask64_operand" "S")) (const_int 0))) - (clobber (match_scratch:DI 4 "=r,r"))] + (clobber (match_scratch:DI 4 "=r"))] "TARGET_POWERPC64" - "@ - rld%I2c%B3. %4,%1,%H2,%S3 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (match_operand:DI 3 "mask64_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 4 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 4) - (and:DI - (rotate:DI (match_dup 1) - (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") + "rld%I2c%B3. %4,%1,%H2,%S3" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotldi3_internal6" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (and:DI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) - (match_operand:DI 3 "mask64_operand" "S,S")) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "ri")) + (match_operand:DI 3 "mask64_operand" "S")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWERPC64" - "@ - rld%I2c%B3. %0,%1,%H2,%S3 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (match_operand:DI 3 "mask64_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI - (rotate:DI (match_dup 1) - (match_dup 2)) - (match_dup 3)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (and:DI - (rotate:DI (match_dup 1) - (match_dup 2)) - (match_dup 3))) - (set (match_dup 4) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "rld%I2c%B3. %0,%1,%H2,%S3" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotldi3_internal7" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -6972,82 +4772,29 @@ "rld%I2cl %0,%1,%H2,56") (define_insn "*rotldi3_internal8" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - rld%I2cl. %3,%1,%H2,56 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI - (subreg:QI - (rotate:DI - (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (zero_extend:DI - (subreg:QI - (rotate:DI - (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "rld%I2cl. %3,%1,%H2,56" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotldi3_internal9" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] "TARGET_POWERPC64" - "@ - rld%I2cl. %0,%1,%H2,56 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI - (subreg:QI - (rotate:DI - (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (zero_extend:DI - (subreg:QI - (rotate:DI - (match_dup 1) - (match_dup 2)) 0)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (zero_extend:DI - (subreg:QI - (rotate:DI - (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "rld%I2cl. %0,%1,%H2,56" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotldi3_internal10" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -7059,82 +4806,29 @@ "rld%I2cl %0,%1,%H2,48") (define_insn "*rotldi3_internal11" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - rld%I2cl. %3,%1,%H2,48 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI - (subreg:HI - (rotate:DI - (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (zero_extend:DI - (subreg:HI - (rotate:DI - (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "rld%I2cl. %3,%1,%H2,48" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotldi3_internal12" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] "TARGET_POWERPC64" - "@ - rld%I2cl. %0,%1,%H2,48 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI - (subreg:HI - (rotate:DI - (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (zero_extend:DI - (subreg:HI - (rotate:DI - (match_dup 1) - (match_dup 2)) 0)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (zero_extend:DI - (subreg:QI - (rotate:DI - (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "rld%I2cl. %0,%1,%H2,48" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotldi3_internal13" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -7146,82 +4840,29 @@ "rld%I2cl %0,%1,%H2,32") (define_insn "*rotldi3_internal14" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - rld%I2cl. %3,%1,%H2,32 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI - (subreg:SI - (rotate:DI - (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (zero_extend:DI - (subreg:SI - (rotate:DI - (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "rld%I2cl. %3,%1,%H2,32" + [(set_attr "type" "delayed_compare")]) (define_insn "*rotldi3_internal15" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] "TARGET_POWERPC64" - "@ - rld%I2cl. %0,%1,%H2,32 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (zero_extend:DI - (subreg:SI - (rotate:DI - (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (zero_extend:DI - (subreg:SI - (rotate:DI - (match_dup 1) - (match_dup 2)) 0)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (zero_extend:DI - (subreg:QI - (rotate:DI - (match_dup 1) - (match_dup 2)) 0))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "rld%I2cl. %0,%1,%H2,32" + [(set_attr "type" "delayed_compare")]) (define_expand "ashldi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -7250,63 +4891,25 @@ [(set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - sld%I2. %3,%1,%H2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ashift:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - + "sld%I2. %3,%1,%H2" + [(set_attr "type" "delayed_compare")]) + (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (ashift:DI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64" - "@ - sld%I2. %0,%1,%H2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ashift:DI (match_dup 1) - (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ashift:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "sld%I2. %0,%1,%H2" + [(set_attr "type" "delayed_compare")]) (define_expand "lshrdi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -7334,63 +4937,25 @@ "srd%I2 %0,%1,%H2") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - srd%I2. %3,%1,%H2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (lshiftrt:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "srd%I2. %3,%1,%H2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (lshiftrt:DI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64" - "@ - srd%I2. %0,%1,%H2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (lshiftrt:DI (match_dup 1) - (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (lshiftrt:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "srd%I2. %0,%1,%H2" + [(set_attr "type" "delayed_compare")]) (define_expand "ashrdi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -7418,189 +4983,66 @@ "srad%I2 %0,%1,%H2") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - srad%I2. %3,%1,%H2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ashiftrt:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "srad%I2. %3,%1,%H2" + [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (ashiftrt:DI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64" - "@ - srad%I2. %0,%1,%H2 - #" - [(set_attr "type" "delayed_compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ashiftrt (match_dup 1) - (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ashiftrt (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_expand "anddi3" - [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:DI 2 "and_operand" "?r,L,K,J"))) - (clobber (match_scratch:CC 3 "=X,X,x,x"))])] - "TARGET_POWERPC64" - "") - -;; If cr0 isn't available, and we want to do an andi, load the register into -;; the destination first. + "srad%I2. %0,%1,%H2" + [(set_attr "type" "delayed_compare")]) -(define_insn "anddi3_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,&??r,&??r") - (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") - (match_operand:DI 2 "and_operand" "?r,L,K,J,K,J"))) - (clobber (match_operand:CC 3 "scratch_operand" "=X,X,x,x,X,X"))] +(define_insn "anddi3" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") + (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) + (clobber (match_scratch:CC 3 "=X,X,x,x"))] "TARGET_POWERPC64" "@ and %0,%1,%2 - {rlinm|rlwinm} %0,%1,0,%m2,%M2 - andil %0,%1,%b2 - andis. %0,%1,%u2 - # - #" - [(set_attr "length" "4,4,4,4,8,8")]) - -(define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "const_int_operand" ""))) - (clobber (scratch:CC))] - "TARGET_POWERPC64 && reload_completed && !mask_constant (INTVAL (operands[2]))" - [(set (match_dup 0) - (match_dup 2)) - (parallel [(set (match_dup 0) - (and:DI (match_dup 0) - (match_dup 1))) - (clobber (scratch:CC))])] - "") - -;; Note to set cr's other than cr0 we do the and immediate and then -;; the test again -- this avoids a mcrf which on the higher end -;; machines causes an execution serialization + rldic%B2 %0,%1,0,%S2 + andi. %0,%1,%b2 + andis. %0,%1,%u2") (define_insn "*anddi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:DI 2 "and_operand" "r,K,J,L,r,K,J,L,K,L")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") + (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") + (match_operand:DI 2 "and64_operand" "r,K,J,S")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,&r,&r")) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))] + (clobber (match_scratch:DI 3 "=r,r,r,r"))] "TARGET_POWERPC64" "@ and. %3,%1,%2 andi. %3,%1,%b2 andis. %3,%1,%u2 - rldic%B2. %3,%1,0,%S2 - # - # - # - # - # - #" - [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare") - (set_attr "length" "4,4,4,4,8,8,8,8,12,12")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "and_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 "")) - (clobber (match_scratch:CC 4 ""))] - "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 3) - (and:DI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + rldic%B2. %3,%1,0,%S2" + [(set_attr "type" "compare,compare,compare,delayed_compare")]) (define_insn "*anddi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:DI 2 "and_operand" "r,K,J,L,r,K,J,L,K,J")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") + (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") + (match_operand:DI 2 "and64_operand" "r,K,J,S")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,&r,&r") - (and:DI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))] + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (and:DI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64" "@ and. %0,%1,%2 andi. %0,%1,%b2 andis. %0,%1,%u2 - rldic%B2 %0,%1,0,%m2,%M2 - # - # - # - # - # - #" - [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare") - (set_attr "length" "4,4,4,4,8,8,8,8,12,12")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "and_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:CC 4 ""))] - "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) - (and:DI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + rldic%B2. %3,%1,0,%S2" + [(set_attr "type" "compare,compare,compare,delayed_compare")]) (define_expand "iordi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -7635,62 +5077,25 @@ oris %0,%1,%u2") (define_insn "*iordi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r") + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - or. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (ior:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "or. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*iordi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r") + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (ior:DI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64" - "@ - or. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ior:DI (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (ior:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "or. %0,%1,%2" + [(set_attr "type" "compare")]) ;; Split an IOR that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. @@ -7741,62 +5146,25 @@ xoris %0,%1,%u2") (define_insn "*xordi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - xor. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (xor:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "xor. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*xordi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (xor:DI (match_dup 1) (match_dup 2)))] "TARGET_POWERPC64" - "@ - xor. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (xor:DI (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (xor:DI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "xor. %0,%1,%2" + [(set_attr "type" "compare")]) ;; Split an XOR that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. @@ -7822,63 +5190,25 @@ "eqv %0,%1,%2") (define_insn "*eqvdi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] - "TARGET_POWERPC64" - "@ - eqv. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" ""))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") + (match_operand:DI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (not:DI (xor:DI (match_dup 1) - (match_dup 2)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + (clobber (match_scratch:DI 3 "=r"))] + "TARGET_POWERPC64" + "eqv. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*eqvdi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") + (match_operand:DI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (not:DI (xor:DI (match_dup 1) (match_dup 2))))] - "TARGET_POWERPC64" - "@ - eqv. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_short_operand" ""))) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (not:DI (xor:DI (match_dup 1) - (match_dup 2))))] - "reload_completed" - [(set (match_dup 0) - (not:DI (xor:DI (match_dup 1) - (match_dup 2)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "TARGET_POWERPC64" + "eqv. %0,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*andcdi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -7888,63 +5218,25 @@ "andc %0,%2,%1") (define_insn "*andcdi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - andc. %3,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (and:DI (not:DI (match_dup 1)) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "andc. %3,%2,%1" + [(set_attr "type" "compare")]) (define_insn "*andcdi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (and:DI (not:DI (match_dup 1)) (match_dup 2)))] "TARGET_POWERPC64" - "@ - andc. %0,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (not:DI (match_dup 1)) - (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (and:DI (not:DI (match_dup 1)) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "andc. %0,%2,%1" + [(set_attr "type" "compare")]) (define_insn "*iorcdi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -7954,196 +5246,81 @@ "orc %0,%2,%1") (define_insn "*iorcdi3_inernal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - orc. %3,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (ior:DI (not:DI (match_dup 1)) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "orc. %3,%2,%1" + [(set_attr "type" "compare")]) (define_insn "*iorcdi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (ior:DI (not:DI (match_dup 1)) (match_dup 2)))] "TARGET_POWERPC64" - "@ - orc. %0,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ior:DI (not:DI (match_dup 1)) - (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (ior:DI (not:DI (match_dup 1)) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "orc. %0,%2,%1" + [(set_attr "type" "compare")]) (define_insn "*nanddi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) + (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))] "TARGET_POWERPC64" "nand %0,%1,%2") (define_insn "*nanddi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) + (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - nand. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (ior:DI (not:DI (match_dup 1)) - (not:DI (match_dup 2)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "nand. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*nanddi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) + (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] "TARGET_POWERPC64" - "@ - nand. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ior:DI (not:DI (match_dup 1)) - (not:DI (match_dup 2))))] - "reload_completed" - [(set (match_dup 0) - (ior:DI (not:DI (match_dup 1)) - (not:DI (match_dup 2)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") + "nand. %0,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*nordi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) + (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))] "TARGET_POWERPC64" "nor %0,%1,%2") (define_insn "*nordi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) + (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (clobber (match_scratch:DI 3 "=r"))] "TARGET_POWERPC64" - "@ - nor. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (and:DI (not:DI (match_dup 1)) - (not:DI (match_dup 2)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") + "nor. %3,%1,%2" + [(set_attr "type" "compare")]) (define_insn "*nordi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x") + (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) + (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] "TARGET_POWERPC64" - "@ - nor. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (not:DI (match_dup 1)) - (not:DI (match_dup 2))))] - "reload_completed" - [(set (match_dup 0) - (and:DI (not:DI (match_dup 1)) - (not:DI (match_dup 2)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - + "nor. %0,%1,%2" + [(set_attr "type" "compare")]) ;; Now define ways of moving data around. @@ -8409,42 +5586,13 @@ }") (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] "" - "@ - mr. %0,%1 - #" + "mr. %0,%1" [(set_attr "type" "compare")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (match_dup 1))] - "reload_completed && rtx_equal_p (operands[0], operands[1])" - [(set (match_dup 2) - (compare:CC (match_dup 1) - (const_int 0)))] - "") - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (match_dup 1))] - "reload_completed && !rtx_equal_p (operands[0], operands[1])" - [(set (match_dup 2) - (compare:CC (match_dup 1) - (const_int 0))) - (set (match_dup 0) - (match_dup 1))] - "") - (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") @@ -9180,41 +6328,13 @@ }") (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] "TARGET_POWERPC64" - "@ - mr. %0,%1 - #" + "mr. %0,%1" [(set_attr "type" "compare")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (match_dup 1))] - "reload_completed && rtx_equal_p (operands[0], operands[1])" - [(set (match_dup 2) - (compare:CC (match_dup 1) - (const_int 0)))] - "") - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") - (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (match_dup 1))] - "reload_completed && !rtx_equal_p (operands[0], operands[1])" - [(set (match_dup 2) - (compare:CC (match_dup 1) - (const_int 0))) - (set (match_dup 0) - (match_dup 1))] - "") ;; TImode is similar, except that we usually want to compute the address into ;; a register and use lsi/stsi (the exception is during reload). MQ is also @@ -11442,52 +8562,42 @@ [(set_attr "length" "12,8,12,12,12")]) (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") (compare:CC - (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") (eq:SI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] "" "@ xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 - {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 - xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 - {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1\;cmpli %4,%0,0 - {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0\;cmpli %4,%0,0 - {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0\;cmpli %4,%0,0 - {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0\;cmpli %4,%0,0" + {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0" [(set_attr "type" "compare") - (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) + (set_attr "length" "12,8,12,12,12")]) (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") (compare:CC - (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) + (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") + (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") (eq:DI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] "TARGET_POWERPC64" "@ xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 subfic %3,%1,0\;adde. %0,%3,%1 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 - subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 - xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 - subfic %3,%1,0\;adde %0,%3,%1\;cmpli %4,%0,0 - xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0\;cmpli %4,%0,0 - xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0\;cmpli %4,%0,0 - subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0\;cmpli %4,%0,0" + subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0" [(set_attr "type" "compare") - (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) + (set_attr "length" "12,8,12,12,12")]) ;; We have insns of the form shown by the first define_insn below. If ;; there is something inside the comparison operation, we must split it. @@ -11520,54 +8630,44 @@ [(set_attr "length" "12,8,12,12,12")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") (compare:CC (plus:SI - (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) + (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] "" "@ xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 - {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 + {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 - {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 - xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3\;cmpli %0,%4,0 - {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3\;cmpli %0,%4,0 - {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0 - {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0 - {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0" + {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" [(set_attr "type" "compare") - (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) + (set_attr "length" "12,8,12,12,12")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") (compare:CC (plus:SI - (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) + (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] "" "@ xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 - {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 - xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0 - {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3\;cmpli %5,%0,0 - {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0 - {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0 - {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0" + {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" [(set_attr "type" "compare") - (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) + (set_attr "length" "12,8,12,12,12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") @@ -11626,74 +8726,66 @@ [(set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (plus:SI (lshiftrt:SI - (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) (const_int 31)) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=&r,&r"))] + (clobber (match_scratch:SI 3 "=&r"))] "" - "@ - {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 - {ai|addic} %3,%1,-1\;{aze|addze} %3,%2\;cmpli %0,%3,0" + "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) + (set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (plus:DI (lshiftrt:DI - (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) + (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) (const_int 63)) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:DI 3 "=&r,&r"))] + (clobber (match_scratch:DI 3 "=&r"))] "TARGET_POWERPC64" - "@ - addic %3,%1,-1\;addze. %3,%2 - addic %3,%1,-1\;addze. %3,%2\;cmpdi %0,%3,0" + "addic %3,%1,-1\;addze. %3,%2" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) + (set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (plus:SI (lshiftrt:SI - (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) (const_int 31)) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) (match_dup 2))) - (clobber (match_scratch:SI 3 "=&r,&r"))] + (clobber (match_scratch:SI 3 "=&r"))] "" - "@ - {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 - {ai|addic} %3,%1,-1\;{aze|addze} %0,%2\;cmpli %4,%0,0" + "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) + (set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (plus:DI (lshiftrt:DI - (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) + (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) (const_int 63)) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) + (match_operand:DI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) (match_dup 2))) - (clobber (match_scratch:DI 3 "=&r,&r"))] + (clobber (match_scratch:DI 3 "=&r"))] "TARGET_POWERPC64" - "@ - addic %3,%1,-1\;addze. %0,%2 - addic %3,%1,-1\;addze. %0,%2\;cmpdi %4,%0,0" + "addic %3,%1,-1\;addze. %0,%2" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -11707,22 +8799,20 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") (compare:CC - (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) + (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_short_operand" "r,O")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (le:SI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:SI 3 "=r,X,r,X"))] + (clobber (match_scratch:SI 3 "=r,X"))] "TARGET_POWER" "@ doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 - {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 - doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3\;cmpli %4,%0,0 - {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31\;cmpli %4,%0,0" - [(set_attr "type" "compare,delayed_compare,compare,compare") - (set_attr "length" "12,12,16,16")]) + {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31" + [(set_attr "type" "compare,delayed_compare") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -11737,40 +8827,36 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) + (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_short_operand" "r,O")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r"))] "TARGET_POWER" "@ doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 - {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 - doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0 - {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3\;cmpli %0,%4,0" + {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3" [(set_attr "type" "compare") - (set_attr "length" "12,12,16,16")]) + (set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) + (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_short_operand" "r,O")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r"))] "TARGET_POWER" "@ doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 - {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3 - doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3\;cmpli %5,%0,0 - {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3\;cmpli %5,%0,0" + {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3" [(set_attr "type" "compare") - (set_attr "length" "12,12,16,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -11791,19 +8877,17 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (leu:SI (match_dup 1) (match_dup 2)))] "" - "@ - {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 - {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0\;cmpli %3,%0,0" + "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -11816,36 +8900,32 @@ [(set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) - (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (clobber (match_scratch:SI 4 "=&r"))] "" - "@ - {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 - {sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %4,%3\;cmpli %0,%4,0" + "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) + (set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) - (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (clobber (match_scratch:SI 4 "=&r"))] "" - "@ - {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3 - {sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3\;cmpli %5,%0,0" + "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -11867,38 +8947,34 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (and:SI (neg:SI - (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) - (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI"))) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (clobber (match_scratch:SI 4 "=&r"))] "" - "@ - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %4,%3,%4\;cmpli %0,%4,0" + "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC (and:SI (neg:SI - (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) - (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI"))) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (clobber (match_scratch:SI 4 "=&r"))] "" - "@ - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4\;cmpli %5,%0,0" + "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -11909,19 +8985,17 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) + (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (lt:SI (match_dup 1) (match_dup 2)))] "TARGET_POWER" - "@ - doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 - doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31\;cmpli %3,%0,0" - [(set_attr "type" "delayed_compare,compare") - (set_attr "length" "12,16")]) + "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" + [(set_attr "type" "delayed_compare") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -11934,36 +9008,32 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) - (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (clobber (match_scratch:SI 4 "=&r"))] "TARGET_POWER" - "@ - doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 - doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %4,%3\;cmpli %0,%4,0" + "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) - (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (clobber (match_scratch:SI 4 "=&r"))] "TARGET_POWER" - "@ - doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 - doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3\;cmpli %5,%0,0" + "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -11984,21 +9054,19 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") (compare:CC - (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) + (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ltu:SI (match_dup 1) (match_dup 2)))] "" "@ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 - {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 - {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0\;cmpli %3,%0,0 - {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0\;cmpli %3,%0,0" + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" [(set_attr "type" "compare") - (set_attr "length" "12,12,16,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") @@ -12015,40 +9083,36 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) + (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %4,%4,%3\;cmpli %0,%4,0 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %4,%4,%3\;cmpli %0,%4,0" + {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" [(set_attr "type" "compare") - (set_attr "length" "12,12,16,16")]) + (set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) + (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %0,%4,%3\;cmpli %5,%0,0 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %0,%4,%3\;cmpli %5,%0,0" + {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" [(set_attr "type" "compare") - (set_attr "length" "12,12,16,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -12070,20 +9134,18 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) + (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ge:SI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:SI 3 "=r,r"))] + (clobber (match_scratch:SI 3 "=r"))] "TARGET_POWER" - "@ - doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 - doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3\;cmpli %4,%0,0" + "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -12096,36 +9158,32 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) - (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (clobber (match_scratch:SI 4 "=&r"))] "TARGET_POWER" - "@ - doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 - doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0" + "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) - (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (clobber (match_scratch:SI 4 "=&r"))] "TARGET_POWER" - "@ - doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 - doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3\;cmpli %5,%0,0" + "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -12149,42 +9207,38 @@ [(set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (and:SI (neg:SI (lshiftrt:SI - (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 31))) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=&r,&r"))] + (clobber (match_scratch:SI 3 "=&r"))] "" - "@ - {srai|srawi} %3,%1,31\;andc. %3,%2,%3 - {srai|srawi} %3,%1,31\;andc %3,%2,%3\;cmpli %0,%3,0" + "{srai|srawi} %3,%1,31\;andc. %3,%2,%3" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) + (set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (and:SI (neg:SI (lshiftrt:SI - (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 31))) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) (const_int 31))) (match_dup 2))) - (clobber (match_scratch:SI 3 "=&r,&r"))] + (clobber (match_scratch:SI 3 "=&r"))] "" - "@ - {srai|srawi} %3,%1,31\;andc. %0,%2,%3 - {srai|srawi} %3,%1,31\;andc %0,%2,%3\;cmpli %4,%0,0" + "{srai|srawi} %3,%1,31\;andc. %0,%2,%3" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -12197,21 +9251,19 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") (compare:CC - (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (geu:SI (match_dup 1) (match_dup 2)))] "" "@ {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 - {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 - {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0\;cmpli %3,%0,0 - {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0\;cmpli %3,%0,0" + {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" [(set_attr "type" "compare") - (set_attr "length" "12,12,16,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -12226,40 +9278,36 @@ [(set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) + (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 - {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 - {sf|subfc} %4,%2,%1\;{aze|addze} %4,%3\;cmpli %0,%4,0 - {ai|addic} %4,%1,%n2\;{aze|addze} %4,%3\;cmpli %0,%4,0" + {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" [(set_attr "type" "compare") - (set_attr "length" "8,8,12,12")]) + (set_attr "length" "8")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) + (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 - {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 - {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3\;cmpli %5,%0,0 - {ai|addic} %4,%1,%n2\;{aze|addze} %4,%3\;cmpli %5,%0,0" + {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" [(set_attr "type" "compare") - (set_attr "length" "8,8,12,12")]) + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -12285,42 +9333,38 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC (and:SI (neg:SI - (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %4,%3,%4\;cmpli %0,%4,0 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4\;cmpli %0,%4,0" + {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" [(set_attr "type" "compare") - (set_attr "length" "12,12,16,16")]) + (set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC (and:SI (neg:SI - (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4\;cmpli %5,%0,0 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4\;cmpli %5,%0,0" + {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" [(set_attr "type" "compare") - (set_attr "length" "12,12,16,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -12331,19 +9375,17 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 2 "cc_reg_operand" "=x") (compare:CC - (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (gt:SI (match_dup 1) (const_int 0)))] "" - "@ - {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 - {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31\;cmpli %2,%0,0" - [(set_attr "type" "delayed_compare,compare") - (set_attr "length" "12,8")]) + "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31" + [(set_attr "type" "delayed_compare") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -12354,19 +9396,17 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "r,r")) + (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (gt:SI (match_dup 1) (match_dup 2)))] "TARGET_POWER" - "@ - doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 - doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31\;cmpli %3,%0,0" - [(set_attr "type" "delayed_compare,compare") - (set_attr "length" "12,16")]) + "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" + [(set_attr "type" "delayed_compare") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -12379,36 +9419,32 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=&r,&r"))] + (clobber (match_scratch:SI 3 "=&r"))] "" - "@ - {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 - {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %3,%2\;cmpli %0,%3" + "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:SI 3 "=&r,&r"))] + (clobber (match_scratch:SI 3 "=&r"))] "" - "@ - {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 - {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %3,%2\;cmpli %4,%3" + "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -12421,36 +9457,32 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "r,r")) - (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (clobber (match_scratch:SI 4 "=&r"))] "TARGET_POWER" - "@ - doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 - doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %4,%3\;cmpli %0,%4,0" + "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "r,r")) - (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (clobber (match_scratch:SI 4 "=&r"))] "TARGET_POWER" - "@ - doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 - doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3\;cmpli %5,%0,0" + "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -12477,19 +9509,17 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) + (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (gtu:SI (match_dup 1) (match_dup 2)))] "" - "@ - {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 - {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0\;cmpli %3,%0,0" + "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" [(set_attr "type" "compare") - (set_attr "length" "12,16")]) + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") @@ -12505,40 +9535,36 @@ [(set_attr "length" "8,12,12")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) + (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_short_operand" "I,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ - {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 - {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3\;cmpli %0,%4,0 - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3\;cmpli %0,%4,0" + {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 + {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" [(set_attr "type" "compare") - (set_attr "length" "8,12,12,16")]) + (set_attr "length" "8,12")]) (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) - (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) + (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_short_operand" "I,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 - {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3\;cmpli %5,%0,0 - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %0,%4,%3\;cmpli %5,%0,0" + {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" [(set_attr "type" "compare") - (set_attr "length" "8,12,12,16")]) + (set_attr "length" "8,12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |