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| author | Jim Wilson <wilson@gcc.gnu.org> | 1993-01-11 14:26:45 -0800 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1993-01-11 14:26:45 -0800 |
| commit | 26c5587d43c1379f05908779d9f066cde38579e3 (patch) | |
| tree | 95df5f53db057410388304940fc11678eb2ada18 | |
| parent | ab5519b72116dd509ea5cb0d14be6b6341a8a59a (diff) | |
| download | gcc-26c5587d43c1379f05908779d9f066cde38579e3.zip gcc-26c5587d43c1379f05908779d9f066cde38579e3.tar.gz gcc-26c5587d43c1379f05908779d9f066cde38579e3.tar.bz2 | |
(TARGET_SWITCHES): Add no-fpu and hard-float.
(CONDITIONAL_REGISTER_USAGE): Define for ! TARGET_FPU.
(BASE_RETURN_VALUE_REG): Use reg 8 when ! TARGET_FPU.
(BASE_OUTGOING_VALUE_REG): Use reg 24 when ! TARGET_FPU.
From-SVN: r3196
| -rw-r--r-- | gcc/config/sparc/sparc.h | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 3632dcd..e6764db 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -120,6 +120,8 @@ extern int target_flags; #define TARGET_SWITCHES \ { {"fpu", 1}, \ + {"no-fpu", -1}, \ + {"hard-float", 1}, \ {"soft-float", -1}, \ {"epilogue", 2}, \ {"no-epilogue", -2}, \ @@ -300,6 +302,21 @@ extern int target_flags; 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1} +/* If !TARGET_FPU, then make the fp registers fixed so that they won't + be allocated. */ + +#define CONDITIONAL_REGISTER_USAGE \ +do \ + { \ + if (! TARGET_FPU) \ + { \ + int regno; \ + for (regno = 32; regno < 64; regno++) \ + fixed_regs[regno] = 1; \ + } \ + } \ +while (0) + /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE @@ -654,9 +671,9 @@ extern char leaf_reg_backmap[]; /* Some subroutine macros specific to this machine. */ #define BASE_RETURN_VALUE_REG(MODE) \ - ((MODE) == SFmode || (MODE) == DFmode ? 32 : 8) + (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8) #define BASE_OUTGOING_VALUE_REG(MODE) \ - ((MODE) == SFmode || (MODE) == DFmode ? 32 : 24) + (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 24) #define BASE_PASSING_ARG_REG(MODE) (8) #define BASE_INCOMING_ARG_REG(MODE) (24) |