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| author | Joern Rennecke <joern.rennecke@embecosm.com> | 2023-05-19 16:18:42 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-05-19 16:19:51 -0600 |
| commit | 259b4b7d349dd3fd560144bd4617f526458b45dc (patch) | |
| tree | af02364e25755ac8b817151407085277c3dac23e | |
| parent | ae2345285c28549145af203ef8161ff96e2ad877 (diff) | |
| download | gcc-259b4b7d349dd3fd560144bd4617f526458b45dc.zip gcc-259b4b7d349dd3fd560144bd4617f526458b45dc.tar.gz gcc-259b4b7d349dd3fd560144bd4617f526458b45dc.tar.bz2 | |
RISC-V: Remove masking third operand of rotate instructions
Sorry, I forgot the ChangeLog entry for my patch and missed the [v2]
part of the subject.
2023-05-18 Joern Rennecke <joern.rennecke@embecosm.com>
gcc/ChangeLog:
* config/riscv/constraints.md (DsS, DsD): Restore agreement
with shiftm1 mode attribute.
| -rw-r--r-- | gcc/config/riscv/constraints.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index c448e6b..44525b2 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -65,13 +65,13 @@ "@internal 31 immediate" (and (match_code "const_int") - (match_test "ival == 31"))) + (match_test "(ival & 31) == 31"))) (define_constraint "DsD" "@internal 63 immediate" (and (match_code "const_int") - (match_test "ival == 63"))) + (match_test "(ival & 63) == 63"))) (define_constraint "DbS" "@internal" |