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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-06-04 17:25:03 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-06-05 08:51:06 +0800 |
| commit | 2418cdfcf60b527dbfdabdda8523bf480ff295c4 (patch) | |
| tree | cd70f11dda1274b8895c3a462529e03639657c01 | |
| parent | b48890844d94092fdf6e9c941af4a47b9c0ce982 (diff) | |
| download | gcc-2418cdfcf60b527dbfdabdda8523bf480ff295c4.zip gcc-2418cdfcf60b527dbfdabdda8523bf480ff295c4.tar.gz gcc-2418cdfcf60b527dbfdabdda8523bf480ff295c4.tar.bz2 | |
RISC-V: Split arguments of expand_vec_perm
Since the following patch will calls expand_vec_perm with
splitted arguments, change the expand_vec_perm interface in
this patch.
gcc/ChangeLog:
* config/riscv/autovec.md: Split arguments.
* config/riscv/riscv-protos.h (expand_vec_perm): Ditto.
* config/riscv/riscv-v.cc (expand_vec_perm): Ditto.
| -rw-r--r-- | gcc/config/riscv/autovec.md | 3 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv-protos.h | 2 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv-v.cc | 6 |
3 files changed, 4 insertions, 7 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 4fe0e32..9f4492d 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -96,7 +96,8 @@ (match_operand:<VINDEX> 3 "vector_perm_operand")] "TARGET_VECTOR && GET_MODE_NUNITS (<MODE>mode).is_constant ()" { - riscv_vector::expand_vec_perm (operands); + riscv_vector::expand_vec_perm (operands[0], operands[1], + operands[2], operands[3]); DONE; } ) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index d032f56..00e1b20 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -241,7 +241,7 @@ opt_machine_mode get_mask_mode (machine_mode); void expand_vec_series (rtx, rtx, rtx); void expand_vec_init (rtx, rtx); void expand_vcond (rtx *); -void expand_vec_perm (rtx *); +void expand_vec_perm (rtx, rtx, rtx, rtx); /* Rounding mode bitfield for fixed point VXRM. */ enum vxrm_field_enum { diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 75cf00b..382f95c 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2024,12 +2024,8 @@ emit_vlmax_masked_gather_mu_insn (rtx target, rtx op, rtx sel, rtx mask) /* Implement vec_perm<mode>. */ void -expand_vec_perm (rtx *operands) +expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel) { - rtx target = operands[0]; - rtx op0 = operands[1]; - rtx op1 = operands[2]; - rtx sel = operands[3]; machine_mode data_mode = GET_MODE (target); machine_mode sel_mode = GET_MODE (sel); |